參數(shù)資料
型號(hào): MFRC50001T
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Highly integrated ISO-IEC 14443 A reader IC
封裝: MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,;
文件頁(yè)數(shù): 49/110頁(yè)
文件大?。?/td> 841K
代理商: MFRC50001T
MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
49 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
10.5.2.3
ErrorFlag register
Error flags show the error status of the last executed command.
Table 51.
Bit
Symbol
Access
Table 52.
Bit
7
6
ErrorFlag register (address: 0Ah) reset value: 0100 0000b, 40h bit allocation
7
6
5
4
0
KeyErr
AccessErr
FIFOOvfl
R
R
R
R
3
2
1
0
CRCErr
R
FramingErr
R
ParityErr
R
CollErr
R
ErrorFlag register bit descriptions
Symbol
Value
0
-
KeyErr
1
Description
reserved
set when the LoadKeyE2 or LoadKey command recognize that the
input data is not encoded based on the key format definition
set when the LoadKeyE2 or the LoadKey command starts
set when the access rights to the EEPROM are violated
set when an EEPROM related command starts
set when the microprocessor or MFRC500 internal state machine
(e.g. receiver) tries to write data to the FIFO buffer when it is full
set when RxCRCEn is set and the CRC fails
automatically set during the PrepareRx state in the receiver start
phase
set when the SOF is incorrect
automatically set during the PrepareRx state in the receiver start
phase
set when the parity check fails
automatically set during the PrepareRx state in the receiver start
phase
set when a bit-collision is detected
automatically set during the PrepareRx state in the receiver start
phase
0
1
0
1
5
AccessErr
4
FIFOOvfl
3
CRCErr
1
0
2
FramingErr
1
0
1
ParityErr
1
0
0
CollErr
1
0
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