參數(shù)資料
型號(hào): MCZ33989EG
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類: CAN
英文描述: System Basis Chip with High-Speed CAN Transceiver
中文描述: 系統(tǒng)基礎(chǔ)芯片高高速CAN收發(fā)器
文件頁數(shù): 54/66頁
文件大?。?/td> 1181K
代理商: MCZ33989EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
54
33989
TYPICAL APPLICATIONS
SUPPLEMENTAL APPLICATION NOTES
Figure 46. Node is in Bus Off State
SOFTWARE ASPECTS
Introduction
This section describes the MC33989 operation and the
microcontroller SPI software routine that has to be executed
in order to control the device. Structure of the Byte: ADR
(3 bits) + R/W (1bit) + DATA (4 bits). MSB is sent first. Refer
to MC33989 specifications for more details.
The DC current can be calculated as follows:
Idc= (Time in dominant * peak current of the fault) / total error frame time
Idc= (17+15)*peak current / ((23*15)+1408)=32 / 1753*peak current
Example for CANL2Vbat (peak current = - 240 mA): Idc = 32*(-) 240 / 1753=(-)4.38 mA
TX
RX
Rx is driven only during the glitch occuring on the CAN bus (the dominant time is shorter than a bit time)
TEC=128: the node reaches the error passive level
23 recessive bits: CAN passive error frame
Node sends one dominant bit. As there is still the fault, the TEC is incremented by 8 each time.
128 occurrences of 11 recessive bits
BUS OFF is recover
TEC reaches 255: the node is BUS OFF
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相關(guān)代理商/技術(shù)參數(shù)
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MCZ33989EG 制造商:Freescale Semiconductor 功能描述:IC SYSTEM BASIS W/CAN TRANCEIVER
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