參數(shù)資料
型號: MCZ33989EG
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類: CAN
英文描述: System Basis Chip with High-Speed CAN Transceiver
中文描述: 系統(tǒng)基礎(chǔ)芯片高高速CAN收發(fā)器
文件頁數(shù): 34/66頁
文件大小: 1181K
代理商: MCZ33989EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
34
33989
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Wake-up Input Register (WUR)
The local wake-up inputs, L0, L1, L2, and L3 can be used
in both Normal and Standby modes as port expander, as well
as and for waking up the SBC in Sleep or Stop modes.
Please see
Table 21
.
The wake-up inputs can be configured separately, while
L0 and L1 are configured together. Bits L2 and L3 are
configured together. Please see
Table 22
.
Table 23
provides Status bits data.
Table 20. IOR Status Bits
Status Bit
Description
V2LOW
V2 Below 4.0 V
HS1OT
High Side 1 Over Temperature
VSUPLOW
V
SUP
Below 6.1 V
If Set, SBC Accepts Command to go to Debug Modes (No WD)
DEBUG
Table 21. WUR Register
WUR
D3
D2
D1
D0
$100B
W
LCTR3
LCTR2
LCTR1
LCTR0
R
L3WU
L2WU
L1WU
L0WU
Reset Value
0
0
0
0
Reset Condition
POR, NR2R, N2R, STB2R, STO2R
Table 22. WUR Control Bits
LCTR3
LCTR2
LCTR1
LCTR0
L0/L1 Config
L2/L3 Config
x
x
0
0
Inputs Disabled
x
x
0
1
High Level Sensitive
x
x
1
0
Low Level Sensitive
x
x
1
1
Both Level Sensitive
0
0
x
x
Inputs Disabled
0
1
x
x
High Level Sensitive
1
0
x
x
Low Level Sensitive
1
1
x
x
Both Level Sensitive
Table 23. WUR Status Bits
Status Bit
Description
L3WU
Wake-up Occurred (Sleep/Stop Modes), Logic State on Lx (Standby/Normal Modes)
L2WU
L1WU
L0WU
Notes: Status bits have two functions. After SBC wake-up, they indicate the wake-up source (Example: L2WU set at 1 if wake-up source is L2
input). After SBC wake and once the WUR has been read, status bits indicates the real time state of the LX inputs (1 mean LX is above
threshold, 0 means that LX input is below threshold).
If, after a wake-up from LX input, a WD timeout occurs before the first reading of the WUR register, the LXxWU bits are reset. This can occur
only if SBC was in Stop mode.
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