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Analog Integrated Circuit Device Data
Freescale Semiconductor
17
33989
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
Figure 8. SPI Timing Characteristics
Di 0
Do 0
Undefined
Don’t Care
Di 8
Don’t Care
t
LEAD
t
SIH
t
SISU
t
LAG
t
PCLK
t
WCLKH
t
WCLKL
t
VALID
Do 8
t
SODIS
CS
SCLK
MOSI
MISO
t
SOEN
Incoming data at MOSI pin is sampled by the SBC at SCLK falling edge.
Outgoing data at MISO pin is set by the SBC at SCLK rising edge (after t
VALID
delay time).
Notes: