參數(shù)資料
型號(hào)： MCR705JP7CDWE
廠商： Freescale Semiconductor
文件頁數(shù)： 97/164頁
文件大?。?/td> 0K
描述： MCU 8BIT 224B RAM 28-SOIC
標(biāo)準(zhǔn)包裝： 26
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 22
程序存儲(chǔ)器容量： 6KB（6K x 8）
程序存儲(chǔ)器類型： OTP
RAM 容量： 224 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
Interrupts
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
38
Freescale Semiconductor
With the edge-sensitive only trigger MOR option, a rising edge on a PA0:3 pin latches an external interrupt
request. A subsequent external interrupt request can be latched only after the voltage level of the previous
interrupt signal returns to a logic 0 and then rises again to a logic 1.
NOTE
If the port A pins are enabled as external interrupts, then a high level on any
PA0:3 pin will drive the state of the IRQ function such that the IRQ/VPP pin
and other PA0:3 pins are to be ignored until ALL of the PA0:3 pins have
returned to a low level. Similarly, if the IRQ/VPP pin is at a low level, the
PA0:3 pins will be ignored until the IRQ/VPP pin returns to a high state.
4.5.3 IRQ Status and Control Register (ISCR)
The IRQ status and control register (ISCR), shown in Figure 4-4, contains an external interrupt mask
(IRQE), an external interrupt flag (IRQF), and a flag reset bit (IRQR). Unused bits will read as logic 0s.
The ISCR also contains two control bits for the oscillators, external pin oscillator, and internal low-power
oscillator. Reset sets the IRQE and OM2 bits and clears all the other bits.
IRQE — External Interrupt Request Enable Bit
This read/write bit enables external interrupts. Reset sets the IRQE bit.
1 = External interrupt processing enabled
0 = External interrupt processing disabled
OM1 and OM2 — Oscillator Select Bits
These bits control the selection and enabling of the oscillator source for the MCU. One choice is the
internal low-power oscillator (LPO). The other choice is the external pin oscillator (EPO) which is
common to most M68HC05 MCU devices. The EPO uses external components like filter capacitors
and a crystal or ceramic resonator and consumes more power. The selection and enable conditions
for these two oscillators are shown in Table 4-2.
Address:
$000D
Bit 7
654321
Bit 0
Read:
IRQE
OM2
OM1
0
IRQF
000
Write:
R
IRQR
Reset:
110000
U
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 4-4. IRQ Status and Control Register (ISCR)
Table 4-2. Oscillator Selection
OM2
OM1
Oscillator
Selected
by CPU
Internal
Low-Power
Oscillator
(LPO)
External Pin
Oscillator
(EPO)
Power
Consumption
0
Internal
Enabled
Disabled
Lowest
0
1
External
Disabled
Enabled
Normal
1
0
Internal
Enabled
Disabled
Lowest
1
Internal
Enabled
Normal
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