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參數(shù)資料
型號： MCR705JP7CDWE
廠商： Freescale Semiconductor
文件頁數(shù)： 104/164頁
文件大?。?/td> 0K
描述： MCU 8BIT 224B RAM 28-SOIC
標(biāo)準(zhǔn)包裝： 26
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 6KB（6K x 8）
程序存儲器類型： OTP
RAM 容量： 224 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
Resets
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
44
Freescale Semiconductor
5.2 Power-On Reset
A positive transition on the VDD pin generates a power-on reset. The power-on reset is strictly for
conditions during powering up and cannot be used to detect drops in power supply voltage.
A delay of 16 or 4064 internal bus cycles (tcyc) after the oscillator becomes active allows the clock
generator to stabilize. If the RESET pin is at logic 0 at the end of this multiple tcyc time, the MCU remains
in the reset condition until the signal on the RESET pin goes to a logic 1.
5.3 External Reset
A logic 0 applied to the RESET pin for a minimum of one and one half tcyc generates an external reset.
This pin is connected to a Schmitt trigger input gate to provide an upper and lower threshold voltage
separated by a minimum amount of hysteresis. The external reset occurs whenever the RESET pin is
pulled below the lower threshold and remains in reset until the RESET pin rises above the upper
threshold. This active low input will generate the internal RST signal that resets the CPU and peripherals.
The RESET pin can also be pulled to a low state by an internal pulldown device that is activated by three
internal reset sources. This reset pulldown device will only be asserted for three to four cycles of the
internal bus or as long as the internal reset source is asserted.
NOTE
Do not connect the RESET pin directly to VDD, as this may overload some
power supply designs if the internal pulldown on the RESET pin should
activate. If an external reset function is not required, the RESET pin should
be left unconnected.
5.4 Internal Resets
The four internally generated resets are:
Initial power-on reset (POR) function
COP watchdog timer reset
Low-voltage reset (LVR)
Illegal address detector
Only the COP watchdog timer reset, low-voltage reset, and illegal address detector will also assert the
pulldown device on the RESET pin for the duration of the reset function or for three to four internal bus
cycles, whichever is longer.
5.4.1 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator to stabilize. The POR is strictly
for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out); that
function can be performed by the LVR. Depending on the DELAY bit in the mask option register (MOR),
there is an oscillator stabilization delay of 16 or 4064 internal bus cycles after the LPO becomes active.
The POR will generate the RST signal which will reset the CPU. If any other reset function is active at the
end of the 16- or 4064-cycle delay, the RST signal will remain in the reset condition until the other reset
condition(s) end.
POR will not activate the pulldown device on the RESET pin. VDD must drop below VPOR for the internal
POR circuit to detect the next rise of VDD.
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