參數(shù)資料
型號： MCR705JP7CDWE
廠商： Freescale Semiconductor
文件頁數(shù)： 105/164頁
文件大?。?/td> 0K
描述： MCU 8BIT 224B RAM 28-SOIC
標(biāo)準(zhǔn)包裝： 26
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 6KB（6K x 8）
程序存儲器類型： OTP
RAM 容量： 224 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
Internal Resets
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
45
5.4.2 Computer Operating Properly (COP) Reset
A timeout of the COP watchdog generates a COP reset. The COP watchdog is part of a software error
detection system and must be cleared periodically to start a new timeout period. To clear the COP
watchdog and prevent a COP reset, write a logic 0 to the COPC bit of the COPR register at location
$1FF0. The COPC bit, shown in Figure 5-2, is a write-only bit.
EPMSEC — EPROM Security(1) Bit
The EPMSEC bit is an EPROM, write-only security bit to protect the contents of the user EPROM code
stored in locations $0700–$1FFF.
OPT — Optional Features Bit
The OPT bit enables two additional features: direct drive by comparator 1 output to PB4 and voltage
offset capability to sample capacitor in analog subsystem.
1 = Optional features enabled
0 = Optional features disabled
NOTE
descriptions of the OPT bit.
COPC — COP Clear Bit
COPC is a write-only bit. Periodically writing a logic 0 to COPC prevents the COP watchdog from
resetting the MCU. Reset clears the COPC bit.
1 = No effect on COP watchdog timer
0 = Reset COP watchdog timer
The COP watchdog reset will assert the pulldown device to pull the RESET pin low for three to four cycles
of the internal bus.
The COP watchdog reset function can be enabled or disabled by programming the COPEN bit in the
MOR.
5.4.3 Low-Voltage Reset (LVR)
The LVR activates the RST reset signal to reset the device when the voltage on the VDD pin falls below
the LVR trip voltage. The LVR will assert the pulldown device to pull the RESET pin low for three to four
cycles of the internal bus.
Address:
$1FF0
Bit 7
6
5
4321
Bit 0
Read:
EPMSEC
OPT
Write:
COPC
Reset:
U
UUUUUUU
= Unimplemented
U = Unaffected
Figure 5-2. COP and Security Register (COPR)
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the EPROM/OTPROM
difficult for unauthorized users.
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