參數(shù)資料
型號: MCR705JP7CDWE
廠商: Freescale Semiconductor
文件頁數(shù): 120/164頁
文件大?。?/td> 0K
描述: MCU 8BIT 224B RAM 28-SOIC
標(biāo)準(zhǔn)包裝: 26
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SIO
外圍設(shè)備: POR,溫度傳感器,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 6KB(6K x 8)
程序存儲器類型: OTP
RAM 容量: 224 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
Port B
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
59
PB0-PB7 — Port B Data Bits
These read/write bits are software programmable. Data direction of each bit is under the control of the
corresponding bit in data direction register B. Reset has no effect on port B data.
7.3.2 Data Direction Register B
The contents of the port B data direction register (DDRB) determine whether each port B pin is an input
or an output. Writing a logic 1 to a DDRB bit enables the output buffer for the associated port B pin. A
DDRB bit set to a logic 1 also disables the pulldown device for that pin. Writing a logic 0 to a DDRB bit
disables the output buffer for the associated port B pin. A reset initializes all DDRB bits to logic 0s,
configuring all port B pins as inputs.
DDRB7–DDRB0 — Port B Data Direction Bits
These read/write bits control port B data direction. Reset clears the bits DDRB7–DDRB0.
1 = Corresponding port B pin configured as output and pulldown device disabled
0 = Corresponding port B pin configured as input
7.3.3 Pulldown Register B
All port B pins can have software programmable pulldown devices enabled or disabled globally by the
SWPDI bit in the MOR. These pulldown devices are individually controlled by the write-only pulldown
register B (PDRB) shown in Figure 7-7. Clearing the PDIB7–PDIB0 bits in the PDRB turns on the pulldown
devices if the port B pin is an input. Reading the PDRB returns undefined results since it is a write-only
register. Reset clears the PDIB7–PDIB0 bits, which turns on all the port B pulldown devices.
PDIB7–PDIB0 — Port B Pulldown Inhibit Bits
Writing to these write-only bits controls the port B pulldown devices. Reading these pulldown register
B bits returns undefined data. Reset clears bits PDIB7–PDIB0.
1 = Corresponding port B pin pulldown device turned off
0 = Corresponding port B pin pulldown device turned on if pin has been programmed by the DDRB
to be an input
Address:
$0005
Bit 7
654321
Bit 0
Read:
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
Write:
Reset:
00000000
Figure 7-6. Data Direction Register B (DDRB)
Address:
$0011
Bit 7
654321
Bit 0
Read:
Write:
PDIB7
PDIB6
PDIB5
PDIB4
PDIB3
PDIB2
PDIB1
DIB0
Reset:
00000000
= Unimplemented
Figure 7-7. Pulldown Register B (PDRB)
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