參數(shù)資料
型號： MCR705JP7CDWE
廠商： Freescale Semiconductor
文件頁數(shù)： 107/164頁
文件大?。?/td> 0K
描述： MCU 8BIT 224B RAM 28-SOIC
標(biāo)準(zhǔn)包裝： 26
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 6KB（6K x 8）
程序存儲器類型： OTP
RAM 容量： 224 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
Reset States
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
47
5.5.4 COP Watchdog
A reset clears the COP watchdog timeout counter.
5.5.5 16-Bit Programmable Timer
A reset has these effects on the 16-bit programmable timer:
Initializes the timer counter registers (TMRH and TMRL) to a value of $FFFC
Initializes the alternate timer counter registers (ACRH and ACRL) to a value of $FFFC
Clears all the interrupt enables and the output level bit (OLVL) in the timer control register (TCR)
Does not affect the input capture edge bit (IEDG) in the TCR
Does not affect the interrupt flags in the timer status register (TSR)
Does not affect the input capture registers (ICRH and ICRL)
Does not affect the output compare registers (OCRH and OCRL)
5.5.6 Serial Interface
A reset has these effects on the serial interface:
Clears all bits in the SIOP control register (SCR)
Clears all bits in the SIOP status register (SSR)
Does not affect the contents of the SIOP data register (SDR)
A reset, therefore, disables the SIOP and leaves the shared port B pins as general I/O. Any pending
interrupt flag is cleared and the SIOP interrupt is disabled. Also the baud rate defaults to the slowest rate.
5.5.7 Analog Subsystem
A reset has these effects on the analog subsystem:
Clears all the bits in the multiplex register (AMUX) bits except the hold switch bit (HOLD) which is
set
Clears all the bits in the analog control register (ACR)
Clears all the bits in the analog status register (ASR)
A reset, therefore, connects the negative input of comparator 2 to the channel selection bus, which is
switched to VSS. Both comparators are set up as non-inverting (a higher positive voltage on the positive
input results in a positive output) and both are powered down. The current source and discharge device
on the PB0/AN0 pin is disabled and powered down. Any analog subsystem interrupt flags are cleared and
the analog interrupt is disabled. Direct drive by comparator 1 to the PB4 pin and the voltage offset to the
sample capacitor are disabled (if both are enabled by the OPT bit being set in the COPR).
5.5.8 External Oscillator and Internal Low-Power Oscillator
A reset presets the oscillator select bits (OM1 and OM2) in the interrupt status and control register (ISCR)
such that the device runs from the internal oscillator (OM1 = 0, OM2 = 1) which has these effects on the
oscillators:
The internal low-power oscillator is enabled and selected.
The external oscillator is disabled.
The CPU bus clock is driven from the internal low-power oscillator.
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