參數(shù)資料
型號(hào)： MCR705JP7CDWE
廠商： Freescale Semiconductor
文件頁數(shù)： 25/164頁
文件大?。?/td> 0K
描述： MCU 8BIT 224B RAM 28-SOIC
標(biāo)準(zhǔn)包裝： 26
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 22
程序存儲(chǔ)器容量： 6KB（6K x 8）
程序存儲(chǔ)器類型： OTP
RAM 容量： 224 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
EPROM/OTPROM
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
120
Freescale Semiconductor
ELAT — EPROM Bus Latch Bit
This read/write bit configures address and data buses for programming the EPROM array. EPROM
data cannot be read when ELAT is set. Clearing the ELAT bit also clears the EPGM bit. Reset clears
ELAT.
1 = Address and data buses configured for EPROM programming of the array. The address and
data buses are latched in the EPROM array when a subsequent write to the array is made. Data
in the EPROM array cannot be read.
0 = Address and data buses configured for normal operation
Whenever the ELAT bit is cleared, the EPGM bit is also cleared. Both the EPGM and the ELAT bit cannot
be set using the same write instruction. Any attempt to set both the ELAT and EPGM bit on the same write
instruction cycle will result in the ELAT bit being set and the EPGM bit being cleared. To program a byte
of EPROM, manipulate the EPROG register as follows:
1.
Set the ELAT bit in the EPROG register.
2.
Write the desired data to the desired EPROM address.
3.
Set the EPGM bit in the EPROG register for the specified programming time, tEPGM.
4.
Clear the ELAT and EPGM bits in the EPROG register.
13.2.2 Mask Option Register
The mask option register (MOR) shown in Figure 13-2 is an EPROM byte that controls eight mask options.
The MOR is unaffected by reset. The erased state of the MOR is $00. The options that can be
programmed by the MOR are:
1.
Port software programmable pulldown devices (enable or disable)
2.
Startup delay after stop (16 or 4064 cycles)
3.
Oscillator shunt resistor (2 M
or open)
4.
STOP instruction (enable or disable)
5.
Low-voltage reset (enable or disable)
6.
Port A external interrupt function (enable or disable)
7.
IRQ trigger sensitivity (edge-triggered only or both edge- and level-triggered)
8.
COP watchdog (enable or disable)
SWPDI — Software Pulldown Inhibit Bit
This EPROM bit inhibits software control of the port A and port B pulldown devices.
1 = Software pulldown inhibited
0 = Software pulldown enabled
Address:
$1FF1
Bit 7
6
5
4321
Bit 0
Read:
SWPDI
DELAY
OSCRES
SWAIT
LVREN
PIRQ
LEVEL
COPEN
Write:
Reset:
Unaffected by reset
Erased:
0
00000
Figure 13-2. Mask Option Register (MOR)
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