
xxxvi
MCF5272 User’s Manual
MOTOROLA
TABLES
Table
Number
Title
Page
Number
19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
20-1
20-2
20-3
20-4
20-5
20-6
20-7
21-1
21-2
23-1
23-2
23-3
23-4
23-5
23-6
23-7
23-8
23-9
23-10
23-11
23-12
23-13
23-14
23-15
23-16
23-17
23-18
23-19
23-20
23-21
23-22
23-23
23-24
23-25
A-1
Byte Strobe Operation for 32-Bit Data Bus..............................................................19-20
Byte Strobe Operation for 16-Bit Data Bus—SRAM Cycles..................................19-20
Byte Strobe Operation for 16-Bit Data Bus—SDRAM Cycles...............................19-20
Connecting BS[3:0] to DQMx..................................................................................19-21
Processor Status Encoding........................................................................................19-38
MCF5272 Bus Width Selection................................................................................19-39
MCF5272 CS0 Memory Bus Width Selection.........................................................19-39
MCF5272 High Impedance Mode Selection............................................................19-39
ColdFire Bus Signal Summary..................................................................................20-1
Chip Select Memory Address Decoding Priority.......................................................20-4
Byte Strobe Operation for 32-Bit Data Bus................................................................20-6
Byte Strobe Operation for 16-Bit Data Bus—SRAM Cycles....................................20-7
Byte Strobe Operation for 16-Bit Data Bus—SDRAM Cycles.................................20-7
Data Bus Requirement for Read/Write Cycles...........................................................20-8
External Bus Interface Codes for CSBRs...................................................................20-8
JTAG Signals..............................................................................................................21-3
Instructions..................................................................................................................21-7
Maximum Supply, Input Voltage and Storage Temperature......................................23-1
Operating Temperature...............................................................................................23-2
Thermal Resistance.....................................................................................................23-2
DC Electrical Specifications......................................................................................23-3
I/O Driver Capability..................................................................................................23-3
Clock Input and Output Timing Specifications..........................................................23-5
Processor Bus Input Timing Specifications................................................................23-6
Processor Bus Output Timing Specifications.............................................................23-8
Debug AC Timing Specification ..............................................................................23-12
SDRAM Interface Timing Specifications.................................................................23-13
MII Receive Signal Timing ......................................................................................23-15
MII Transmit Signal Timing.....................................................................................23-16
MII Async Inputs Signal Timing..............................................................................23-17
MII Serial Management Channel Timing.................................................................23-17
Timer Module AC Timing Specifications................................................................23-18
UART Modules AC Timing Specifications..............................................................23-19
IDL Master Mode Timing, PLIC Ports 1, 2, and 3...................................................23-20
IDL Slave Mode Timing, PLIC Ports 0–3................................................................23-21
GCI Slave Mode Timing, PLIC Ports 0–3................................................................23-22
GCI Master Mode Timing, PLIC PORTs 1, 2, 3......................................................23-23
General-Purpose I/O Port AC Timing Specifications...............................................23-25
USB Interface AC Timing Specifications.................................................................23-25
IEEE 1149.1 (JTAG) AC Timing Specifications .....................................................23-26
QSPI Modules AC Timing Specifications................................................................23-28
PWM Modules AC Timing Specifications...............................................................23-28
On-Chip Module Base Address Offsets from MBAR.................................................A-1