
ILLUSTRATIONS
Figure
Number
15-3
15-4
15-5
15-6
16-1
16-2
16-3
16-4
16-5
16-6
16-7
16-8
16-9
16-10
16-11
16-12
16-13
16-14
16-15
16-16
16-17
16-18
16-19
16-20
16-21
16-22
16-23
16-24
16-25
16-26
16-27
16-28
16-29
16-30
16-31
17-1
17-2
17-3
17-4
17-5
17-6
17-7
18-1
Title
Page
Number
xxviii
MCF5272 User’s Manual
MOTOROLA
Timer Reference Registers (TRR0–TRR3) ................................................................15-4
Timer Capture Registers (TCAP0–TCAP3)...............................................................15-5
Timer Counter (TCN0–TCN3)...................................................................................15-5
Timer Event Registers (TER0–TER3)........................................................................15-5
Simplified Block Diagram..........................................................................................16-1
UART Mode Registers 1 (UMR1n)............................................................................16-5
UART Mode Register 2 (UMR2n).............................................................................16-6
UART Status Registers (USRn)..................................................................................16-7
UART Clock-Select Registers (UCSRn)....................................................................16-9
UART Command Registers (UCRn)..........................................................................16-9
UART Receiver Buffer (URBn)...............................................................................16-11
UART Transmitter Buffers (UTBn) .........................................................................16-12
UART Input Port Change Registers (UIPCRn)........................................................16-12
UART Auxiliary Control Registers (UACRn) .........................................................16-13
UART Interrupt Status/Mask Registers (UISRn/UIMRn)........................................16-13
UART Divider Upper Registers (UDUn).................................................................16-14
UART Divider Lower Registers (UDLn).................................................................16-15
UART Autobaud Upper Registers (UABUn)...........................................................16-15
UART Autobaud Lower Registers (UABLn)...........................................................16-15
UART Transmitter FIFO Registers (UTFn).............................................................16-16
UART Receiver FIFO Registers (URFn) .................................................................16-16
UART Fractional Precision Divider Control Registers (UFPDn) ............................16-17
UART Input Port Registers (UIPn)...........................................................................16-18
UART Output Port Command Registers (UOP1/UOP0)..........................................16-18
UART Block Diagram Showing External and Internal Interface Signals................16-19
UART/RS-232 Interface...........................................................................................16-20
Clocking Source Diagram.........................................................................................16-21
Transmitter and Receiver Functional Diagram.........................................................16-23
Transmitter Timing..................................................................................................16-24
Receiver Timing........................................................................................................16-25
Automatic Echo ........................................................................................................16-28
Local Loop-Back ......................................................................................................16-28
Remote Loop-Back...................................................................................................16-29
Multidrop Mode Timing Diagram............................................................................16-30
UART Mode Programming Flowchart.....................................................................16-32
Port A Control Register (PACNT)..............................................................................17-3
Port B Control Register (PBCNT)..............................................................................17-5
Port D Control Register (PDCNT)..............................................................................17-8
Port A Data Direction Register (PADDR)................................................................17-10
Port B Data Direction Register (PBDDR)................................................................17-10
Port C Data Direction Register (PCDDR)................................................................17-11
Port x Data Register (PADAT, PBDAT, and PCDAT)............................................17-11
PWM Block Diagram (3 Identical Modules)..............................................................18-1