
xii
MCF5272 User’s Manual
MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
12.2.1.1
12.2.1.2
12.2.1.3
12.2.1.4
12.2.1.5
12.3
12.3.1
12.3.2
12.3.2.1
12.3.2.2
12.3.2.3
12.3.2.4
12.3.2.5
12.3.2.6
12.3.2.7
12.3.2.8
12.3.2.9
12.3.2.10
12.3.2.11
12.3.2.12
12.3.2.13
12.3.2.14
12.3.2.15
USB Transceiver Interface ....................................................................... 12-4
Clock Generator........................................................................................ 12-4
USB Control Logic................................................................................... 12-4
Endpoint Controllers................................................................................. 12-5
USB Request Processor............................................................................ 12-5
Register Description and Programming Model................................................ 12-7
USB Memory Map........................................................................................ 12-7
Register Descriptions.................................................................................... 12-9
USB Frame Number Register (FNR) ....................................................... 12-9
USB Frame Number Match Register (FNMR)......................................... 12-9
USB Real-Time Frame Monitor Register (RFMR)................................ 12-10
USB Real-Time Frame Monitor Match Register (RFMMR)................. 12-10
USB Function Address Register (FAR) ................................................. 12-11
USB Alternate Settings Register (ASR)................................................. 12-11
USB Device Request Data 1 and 2 Registers (DRR1/ 2)....................... 12-12
USB Specification Number Register (SPECR)...................................... 12-13
USB Endpoint 0 Status Register (EP0SR).............................................. 12-13
USB Endpoint 0 IN Configuration Register (IEP0CFG) ....................... 12-14
USB Endpoint 0 OUT Configuration Register (OEP0CFG).................. 12-15
USB Endpoint 1–7 Configuration Register (EPnCFG).......................... 12-16
USB Endpoint 0 Control Register (EP0CTL) ........................................ 12-16
USB Endpoint 1–7 Control Register (EPnCTL) .................................... 12-19
USB Endpoint 0 Interrupt Mask (EP0IMR) and General/Endpoint 0
Interrupt Registers (EP0ISR).............................................................. 12-20
USB Endpoints 1–7 Status / Interrupt Registers (EPnISR).................... 12-23
USB Endpoint 1–7 Interrupt Mask Registers (EPnIMR)....................... 12-24
USB Endpoint 0–7 Data Registers (EPnDR).......................................... 12-25
USB Endpoint 0–7 Data Present Registers (EPnDPR)........................... 12-25
Configuration RAM.................................................................................... 12-26
Configuration RAM Content.................................................................. 12-26
USB Device Configuration Example...................................................... 12-27
USB Module Access Times........................................................................ 12-28
Registers ................................................................................................. 12-28
Endpoint FIFOs ...................................................................................... 12-28
Configuration RAM................................................................................ 12-28
Software Architecture and Application Notes................................................ 12-28
USB Module Initialization.......................................................................... 12-28
USB Configuration and Interface Changes ................................................ 12-29
FIFO Configuration .................................................................................... 12-29
Data Flow.................................................................................................... 12-30
Control, Bulk, and Interrupt Endpoints .................................................. 12-30
IN Endpoints....................................................................................... 12-31
OUT Endpoints................................................................................... 12-31
12.3.2.16
12.3.2.17
12.3.2.18
12.3.2.19
12.3.3
12.3.3.1
12.3.3.2
12.3.4
12.3.4.1
12.3.4.2
12.3.4.3
12.4
12.4.1
12.4.2
12.4.3
12.4.4
12.4.4.1
12.4.4.1.1
12.4.4.1.2