
CONTENTS
Paragraph
Number
Title
Page
Number
MOTOROLA
Contents
xv
14.4.4
14.4.5
14.5
14.5.1
14.5.2
14.5.3
14.5.4
14.5.5
14.5.6
14.5.7
14.5.8
Transfer Length............................................................................................. 14-8
Data Transfer ................................................................................................ 14-8
Programming Model......................................................................................... 14-9
QSPI Mode Register (QMR) ........................................................................ 14-9
QSPI Delay Register (QDLYR) ................................................................. 14-11
QSPI Wrap Register (QWR)....................................................................... 14-12
QSPI Interrupt Register (QIR).................................................................... 14-12
QSPI Address Register (QAR)................................................................... 14-14
QSPI Data Register (QDR)......................................................................... 14-14
Command RAM Registers (QCR0–QCR15).............................................. 14-14
Programming Example............................................................................... 14-15
Chapter 15
Timer Module
15.1
15.2
15.3
15.3.1
15.3.2
15.3.3
15.3.4
15.3.5
Overview........................................................................................................... 15-1
Timer Operation................................................................................................ 15-2
General-Purpose Timer Registers..................................................................... 15-3
Timer Mode Registers (TMR0–TMR3) ....................................................... 15-3
Timer Reference Registers (TRR0–TRR3) .................................................. 15-4
Timer Capture Registers (TCAP0–TCAP3)................................................. 15-5
Timer Counters (TCN0–TCN3).................................................................... 15-5
Timer Event Registers (TER0–TER3).......................................................... 15-5
Chapter 16
UART Modules
16.1
16.2
16.3
16.3.1
16.3.2
16.3.3
16.3.4
16.3.5
16.3.6
16.3.7
16.3.8
16.3.9
16.3.10
16.3.11
16.3.12
Overview........................................................................................................... 16-1
Serial Module Overview................................................................................... 16-2
Register Descriptions........................................................................................ 16-3
UART Mode Registers 1 (UMR1n).............................................................. 16-5
UART Mode Register 2 (UMR2n)............................................................... 16-6
UART Status Registers (USRn) ................................................................... 16-7
UART Clock-Select Registers (UCSRn)...................................................... 16-8
UART Command Registers (UCRn)............................................................ 16-9
UART Receiver Buffers (URBn) ............................................................... 16-11
UART Transmitter Buffers (UTBn)........................................................... 16-11
UART Input Port Change Registers (UIPCRn).......................................... 16-12
UART Auxiliary Control Registers (UACRn) ........................................... 16-12
UART Interrupt Status/Mask Registers (UISRn/UIMRn).......................... 16-13
UART Divider Upper/Lower Registers (UDUn/UDLn)............................ 16-14
UART Autobaud Registers (UABUn/UABLn).......................................... 16-15