
89
42073A-MCU Wireless-02/13
ATmega2564/1284/644RFR2
The PLL frequency is changed to the transmit frequency within tTR23 = 16 s after
starting the transmit procedure and before starting the transmission. After the
transmission the PLL settles back to the receive frequency within tTR24 = 32 s. This
frequency step does not generate a TRX24_PLL_LOCK or TRX24_PLL_UNLOCK
interrupt within these time spans.
9.6.6.3 Calibration Loops
Due to temperature, supply voltage and part-to-part variations of the radio transceiver
the VCO characteristics diverge. Two automated control loops are implemented to
ensure a stable operation: center frequency (CF) tuning and delay cell (DCU)
calibration. Both calibration loops are initiated automatically when the PLL is enabled
during state transition from TRX_OFF to PLL_ON. The center frequency calibration is
additionally initiated when the PLL changes to a center frequency of another channel.
It is recommended to initiate the calibration loops manually if the PLL operates for a
long time on the same channel e.g. more than 5 min or the operating temperature
changes significantly. Both calibration loops can be initiated manually by setting
PLL_CF_START = 1 of register PLL_CF and PLL_DCU_START = 1 of register
PLL_DCU. The device must be in PLL_ON or RX_ON state to start the calibration. The
completion of the center frequency tuning is indicated by a TRX24_PLL_LOCK
interrupt.
Both calibration loops may be run simultaneously.
9.6.6.4 Interrupt Handling
Two different interrupts indicate the PLL status. The TRX24_PLL_LOCK interrupt
indicates that the PLL has locked. The TRX24_PLL_UNLOCK interrupt indicates an
unexpected unlock condition.
A TRX24_PLL_LOCK interrupt is supposed to occur in the following situations:
State change from TRX_OFF to PLL_ON / RX_ON/ RX_AACK_ON/
TX_ARET_ON;
Channel change in states PLL_ON / RX_ON/ RX_AACK_ON/ TX_ARET_ON;
Any other occurrences of PLL interrupts indicate erroneous behavior and require
checking of the actual device status.
The state transition from BUSY_TX to PLL_ON after successful transmission does not
generate a TRX24_PLL_LOCK interrupt within the settling period.
If a TRX24_PLL_UNLOCK interrupt occurs while the device is receiving/transmitting a
frame the associated interrupts (TRX24_RX_END, TRX24_TX_END) will no happen.
9.6.6.5 RF Channel Selection
The PLL is designed to support 16 channels in the 2.4 GHz ISM band with channel
spacing of 5 MHz according to IEEE 802.15.4. The center frequency of these channels
is defined as follows:
Fc = 2405 + 5 (k – 11) in [MHz], for k = 11, 12 ... 26
where k is the channel number.
The channel k is selected by the CHANNEL bits of register PHY_CC_CCA (see