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型號(hào)：	MC80C52EXXX-16P883D
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40
文件頁(yè)數(shù)：	286/604頁(yè)
文件大小：	22337K
代理商：	MC80C52EXXX-16P883D

42073A-MCU Wireless-02/13

ATmega2564/1284/644RFR2

Register Bits

Description

Set OC2A on Compare Match

Bit 5:4 – COM2B1:0 - Compare Match Output B Mode

These bits control the Output Compare pin (OC2B) behavior. If one or both of the

COM2B1:0 bits are set, the OC2B output overrides the normal port functionality of the

I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit

corresponding to the OC2B pin must be set in order to enable the output driver. When

OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the

WGM22:20 bit settings. The following table shows the COM2B1:0 bit functionality when

the WGM22:20 bits are set to a normal or CTC mode (non-PWM). Refer to section

"Compare Match Output Unit" for a description of the functionality in the other modes.

Table 21-8 COM2B Register Bits

Register Bits

Description

Normal port operation, OC2B disconnected

Toggle OC2B on Compare Match

Clear OC2B on Compare Match

Set OC2B on Compare Match

Bit 3:2 – Res1:0 - Reserved

Bit 1:0 – WGM21:20 - Waveform Generation Mode

Combined with the WGM22 bit found in the TCCR2B Register, these bits control the

counting sequence of the counter, the source for maximum (TOP) counter value, and

what type of waveform generation to be used. Modes of operation supported by the

Timer/Counter2 unit are: Normal mode (counter), Clear Timer on Compare Match

(CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see section

"Modes of Operation" for details).

Table 21-9 WGM2 Register Bits

Register Bits

Description

Normal mode of operation

PWM, phase correct, TOP=0xFF

CTC, TOP = OCRA

Fast PWM, TOP=0xFF

PWM, Phase correct, TOP = OCRA

Fast PWM, TOP=OCRA

21.11.4 TCCR2B – Timer/Counter2 Control Register B

Initial Value

Bit 7 – FOC2A - Force Output Compare A

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