
448
42073A-MCU Wireless-02/13
ATmega2564/1284/644RFR2
conversions take 11 ADC clock cycles.
When a conversion is complete, the result is written to the ADC Data Registers, and
ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software
may then set ADSC again, and a new conversion will be initiated at the earliest after the
following tracking phase. The tracking phase is required after each conversion. Its
duration can be adjusted according to the ADC clock speed by the ADTHT bits in
ADCSRC and is different for single-ended and differential channels. For details see
In Free Running mode, a new conversion will be started immediately after the tracking
phase of the previous conversion while ADSC remains high. The calculation of the
For timing diagrams of single and auto triggered and free running conversions see
Table 27-3. Conversion Start Delay
Channel
Delay from Conversion Start Request to Sample & Hold tSCSMP
Single-Ended
(1)
2 CPU clock cycles
Differential
2 ADC clock cycles
Note:
1. The time tCSMP is between 0…4 CPU clock cycles depending on the ADPS
configuration of register ADCSRA for the ATmega128RFA1
Table 27-4. Tracking Time
Channel
Tracking Phase Duration tTRCK in ADC Clock Cycles
Single-Ended
ADTHT+1, minimum 500 ns
Differential
2ADTHT+3
Table 27-5. Sample Rate in Free Running Mode
Channel
Sample Rate in ADC Clock Cycles
Single-Ended
ADTHT+12
Differential
2ADTHT+14
Figure 27-6. ADC Timing Diagram, Single Conversion
A D C C lo ck
A D E N
A D S C
A D IF
A D C H
A D C L
M U X a n d R E F S U p d a te
1 1 T A DC_CLK
tTR CK
T ra c k in g
C o n v e rsio n
tS CS MP
S ig n a n d M S B o f R e s u lt
L S B o f R e s u lt
M U X a n d R E F S U p d a te
C o n v e rs io n
C o m p le te
tS CS MP
C o n v e rsio n
P re s ca le r R e se t
a n d
S a m p le & H o ld
P re s c a le r
R e se t
a n d
S a m p le
& H o ld