
466
42073A-MCU Wireless-02/13
ATmega2564/1284/644RFR2
Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will
start a conversion on a positive edge of the selected trigger signal. The trigger source is
selected by setting the ADC Trigger Select bits, ADTS in ADCSRB.
Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an A/D conversion is completed and the Data Register are updated.
The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in
SREG are set. ADIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag.
Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be
disabled. This also applies if the SBI and CBI instructions are used.
Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion
Complete Interrupt is activated.
Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the CPU frequency and the input clock
to the ADC.
Table 27-14. ADC Prescaler Selections
ADPS2
ADPS1
ADPS0
Division Factor
0
2
0
1
2
0
1
0
4
0
1
8
1
0
16
1
0
1
32
1
0
64
1
128
27.12.4 ADCSRC – ADC Control and Status Register C
Bit
7
6
5
4
3
2
1
0
NA ($77)
ADTHT1 ADTHT0 ADSUT5
(1)
ADSUT4 ADSUT3 ADSUT2 ADSUT1 ADSUT0
ADCSRC
Read/Write
RW
Initial Value
0
1
0
1
0
1
0
This register defines the track-and-hold time for sampling the analog input voltage of
the ADC and it defines the start-up time for the analog blocks based on a number of
ADC clock cycles. The ADC clock is generated from the system clock with the ADC
prescaler. The bits ADPS2:0 of register ADCSRA set the prescaler ratio. Correct start-
up and track-and-hold times are important for precise conversion results.
Bits 7:6 – ADTHT1:0: ADC Track-and-Hold Time
These bits define the number of ADC clock cycles for the sampling time of the analog