
547
42073A-MCU Wireless-02/13
ATmega2564/1284/644RFR2
Mnemonics
Operands
Description
Operation
Flags
#Clocks
BRSH
k
Branch if Same or Higher
if (C = 0) then PC ← PC + k + 1
None
1 / 2
BRLO
k
Branch if Lower
if (C = 1) then PC ← PC + k + 1
None
1 / 2
BRMI
k
Branch if Minus
if (N = 1) then PC ← PC + k + 1
None
1 / 2
BRPL
k
Branch if Plus
if (N = 0) then PC ← PC + k + 1
None
1 / 2
BRGE
k
Branch if Greater or Equal, Signed
if (N ⊕ V= 0) then
PC ← PC + k + 1
None
1 / 2
BRLT
k
Branch if Less Than Zero, Signed
if (N ⊕ V= 1) then
PC ← PC + k + 1
None
1 / 2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC ← PC + k + 1
None
1 / 2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC ← PC + k + 1
None
1 / 2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC ← PC + k + 1
None
1 / 2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC ← PC + k + 1
None
1 / 2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC ← PC + k + 1
None
1 / 2
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC ← PC + k + 1
None
1 / 2
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC ← PC + k + 1
None
1 / 2
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC ← PC + k + 1
None
1 / 2
34.3 Bit and Bit Test Instructions
Mnemonics
Operands
Description
Operation
Flags
#Clocks
SBI
P,b
Set Bit in I/O Register
I/O(P,b) ← 1
None
2
CBI
P,b
Clear Bit in I/O Register
I/O(P,b) ← 0
None
2
LSL
Rd
Logical Shift Left
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
1
LSR
Rd
Logical Shift Right
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
1
ROL
Rd
Rotate Left Through Carry
Rd(0) ← C, Rd(n+1) ← Rd(n),
C ← Rd(7)
Z,C,N,V
1
ROR
Rd
Rotate Right Through Carry
Rd(7) ← C, Rd(n) ← Rd(n+1),
C ← Rd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0) ← Rd(7..4),
Rd(7..4) ← Rd(3..0)
None
1
BSET
s
Flag Set
SREG(s) ← 1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s) ← 0
SREG(s)
1
BST
Rr, b
Bit Store from Register to T
T ← Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b) ← T
None
1
SEC
Set Carry
C ← 1
C
1
CLC
Clear Carry
C ← 0
C
1
SEN
Set Negative Flag
N ← 1
N
1
CLN
Clear Negative Flag
N ← 0
N
1
SEZ
Set Zero Flag
Z ← 1
Z
1
CLZ
Clear Zero Flag
Z ← 0
Z
1
SEI
Global Interrupt Enable
I ← 1
I
1
CLI
Global Interrupt Disable
I ← 0
I
1