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參數(shù)資料
| 型號(hào)： | MC705C9ACPE |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 62/118頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MCU 2.1MHZ 16K OTP 40-DIP |
| 標(biāo)準(zhǔn)包裝： | 9 |
| 系列： | HC05 |
| 核心處理器： | HC05 |
| 芯體尺寸： | 8-位 |
| 速度： | 2.1MHz |
| 連通性： | SCI，SPI |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 24 |
| 程序存儲(chǔ)器容量： | 16KB（16K x 8） |
| 程序存儲(chǔ)器類(lèi)型： | OTP |
| RAM 容量： | 352 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
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Input/Output (I/O) Ports
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
48
Freescale Semiconductor
7.3 Port B
Port B is an 8-bit bidirectional port. The port B data register is at $0001 and the data direction register
(DDR) is at $0005. The contents of the port B data register are indeterminate at initial powerup and must
be initialized by user software. Reset does not affect the data registers, but clears the data direction
registers, thereby returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port pin to
output mode. Each of the port B pins has an optional external interrupt capability that can be enabled by
programming the corresponding bit in the port B mask option register ($3FF0).
The interrupt option also enables a pullup device when the pin is configured as an input. The edge or
edge- and level-sensitivity of the IRQ pin will also pertain to the enabled port B pins. Care needs to be
taken when using port B pins that have the pullup enabled. Before switching from an output to an input,
the data should be preconditioned to a 1 to prevent an interrupt from occurring. The port B logic is shown
in Figure 7-2.
7.4 Port C
Port C is an 8-bit bidirectional port. The port C data register is at $0002 and the data direction register
(DDR) is at $0006. The contents of the port C data register are indeterminate at initial powerup and must
be initialized by user software. Reset does not affect the data registers, but clears the data direction
registers, thereby returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to
output mode. PC7 has a high current sink and source capability. Figure 7-1 is also applicable to port C.
7.5 Port D
When configured as a C9A, port D is a 7-bit bidirectional port; when configured as a C12A, port D is a
7-bit fixed input port. Four of its pins are shared with the SPI subsystem and two more are shared with
the SCI subsystem. The contents of the port D data register are indeterminate at initial powerup and must
be initialized by user software. During reset all seven bits become valid input ports because the C9A DDR
bits are cleared and the special function output drivers associated with the SCI and SPI subsystems are
disabled, thereby returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to
output mode only when configured as a C9A.
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