參數(shù)資料
型號： MC705C9ACPE
廠商： Freescale Semiconductor
文件頁數(shù)： 35/118頁
文件大?。?/td> 0K
描述： IC MCU 2.1MHZ 16K OTP 40-DIP
標(biāo)準(zhǔn)包裝： 9
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SCI，SPI
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 24
程序存儲器容量： 16KB（16K x 8）
程序存儲器類型： OTP
RAM 容量： 352 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
Functional Pin Descriptions
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
23
1.6.5 RESET
As an input pin, this active low RESET pin is used to reset the MCU to a known startup state by pulling
RESET low. As an output pin, when in MC68HC05C9A mode only, the RESET pin indicates that an
internal MCU reset has occurred. The RESET pin contains an internal Schmitt trigger as part of its input
to improve noise immunity. Refer to
Chapter 5 Resets for more detail.
1.6.6 TCAP
This pin controls the input capture feature for the on-chip programmable timer. The TCAP pin contains an
internal Schmitt trigger as part of its input to improve noise immunity. Refer to Chapter 8
Capture/Compare Timer for more detail.
1.6.7 TCMP
The TCMP pin provides an output for the output compare feature of the on-chip programmable timer.
Refer to Chapter 8 Capture/Compare Timer for more detail.
1.6.8 PA0–PA7
These eight I/O lines comprise port A. The state of each pin is software programmable and all port A pins
are configured as inputs during reset. Refer to Chapter 7 Input/Output (I/O) Ports for more detail.
1.6.9 PB0–PB7
These eight I/O lines comprise port B. The state of each pin is software programmable and all port B pins
are configured as inputs during reset. Port B has mask option register enabled pullup devices and
interrupt capability selectable for any pin. Refer to Chapter 7 Input/Output (I/O) Ports for more detail.
1.6.10 PC0–PC7
These eight I/O lines comprise port C. The state of each pin is software programmable and all port C pins
are configured as inputs during reset. PC7 has high current sink and source capability. Refer to
1.6.11 PD0–PD5 and PD7
These seven I/O lines comprise port D. When configured as a C9A the state of each pin is software
programmable and all port D pins are configured as inputs during reset. When configured as a C12A, the
port D pins are input only. Refer to Chapter 7 Input/Output (I/O) Ports for more detail.
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