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參數(shù)資料
| 型號： | MC705C9ACPE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 26/118頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 2.1MHZ 16K OTP 40-DIP |
| 標(biāo)準(zhǔn)包裝： | 9 |
| 系列： | HC05 |
| 核心處理器： | HC05 |
| 芯體尺寸： | 8-位 |
| 速度： | 2.1MHz |
| 連通性： | SCI，SPI |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 24 |
| 程序存儲器容量： | 16KB（16K x 8） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 352 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
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Configuration Options
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
15
1.3 Configuration Options
The options and functions of the MC68HC705C9A can be configured to emulate either the
MC68HC05C9A or the MC68HC05C12A.
The ROM device MC68HC05C9A has eight ROM mask options to select external interrupt/internal pullup
capability on each of the eight port B bits. Other optional features are controlled by software addressable
registers during operation of the microcontroller. These features are IRQ sensitivity and memory map
configuration.
On the ROM device MC68HC05C12A, all optional features are controlled by ROM mask options. These
features are the eight port B interrupt/pullup options, IRQ sensitivity, STOP instruction disable, and COP
enable.
On the MC68HC705C9A the ROM mask options of the MC68HC05C9A and the MC68HC05C12A are
controlled by mask option registers (MORs). The MORs are EPROM registers which must be
programmed appropriately prior to operation of the microcontroller. The software options of the
MC68HC05C9A are implemented by identical software registers in the MC68HC705C9A.
When configured as an MC68HC05C9A:
The entire 16K memory map of the C9A is enabled, including dual-mapped RAM and EPROM at
locations $0020–$004F and $0100–$017F.
C12A options in the C12MOR ($3FF1) are disabled.
The C9A option register ($3FDF) is enabled, allowing software control over the IRQ sensitivity and
the memory map configuration.
The C9A COP reset register ($001D) and the C9A COP control register ($001E) are enabled,
allowing software control over the C9A COP and clock monitor.
The C12 COP clear register ($3FF0) is disabled.
The port D data direction register ($0007) is enabled, allowing output capability on the seven port
D pins.
SPI output signals (MOSI, MISO, and SCK) require the corresponding bits in the port D data
direction register to be set for output.
The port D wire-OR mode control bit (bit 5 of SPCR $000A) is enabled, allowing open-drain
configuration of port D.
The RESET pin becomes bidirectional; this pin is driven low by a C9A COP or clock monitor
timeout or during power-on reset.
When configured as an MC68HC05C12A:
Memory locations $0100–$0FFF are disabled, creating a memory map identical to the
MC68HC05C12A.
C12A options in the C12MOR ($3FF1) are enabled; these bits control IRQ sensitivity, STOP
instruction disable and C12 COP enable.
The C9A option register ($3FDF) is disabled, preventing software control over the IRQ sensitivity
and the memory map configuration.
The C9A COP reset register ($001D) and the C9A COP control register ($001E) are disabled,
preventing software control over the C9A COP and clock monitor.
The C12 COP clear register ($3FF0) is enabled; this write-only register is used to clear the C12
COP.
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