參數(shù)資料
型號： MC68HC705BD7B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP42
封裝： SDIP-42
文件頁數(shù)： 74/85頁
文件大?。?/td> 302K
代理商： MC68HC705BD7B
MOTOROLA
SECTION 13: ELECTRICAL SPECIFICATIONS
Page 66
GENERAL RELEASE SPECIFICATION
MC68HC05BD7 Rev. 2.0
PRELIMINARY
13.3
DC Electrical Characteristics
(VDD = 5.0 Vdc ±10%, VSS = 0Vdc, TA = 0C to +70C, unless otherwise noted)
NOTES:
1. All values shown reflect average measurements.
2. Typical values at midpoint of voltage range, 25
°C only.
3. Wait IDD: Only timer system and SSP active.
4. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to EXTAL (fOSC = 4.2 MHz),
all inputs 0.2 VDC from rail; no DC loads, less than 50pF on all outputs, CL = 20 pF on EXTAL.
5. Wait IDD: All ports configured as inputs, VIL = 0.2 VDC, VIH = VDD-0.2 VDC.
6. Wait IDD is affected linearly by the EXTAL capacitance.
Characteristic
Symbol
Min
Typ
Max
Unit
Output High Voltage (ILoad = -5.0 mA)
PA0-PA7, PB0-PB1, PC2-PC7, PWM0-PWM7
VOH
VDD–0.8
—
V
Output Low Voltage (ILoad = 5.0 mA for +5V pins and
ILoad = 10.0 mA for +12V open-drain pins)
PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD3, PWM0-
PWM7
VOL
—
0.5
V
Input High Voltage
PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD1, RESET,
IRQ, EXTAL
(TTL Level) VSYNC, HSYNC, SOG
SDA,SCL
VIH
0.8 x VDD
2.0
0.8 x VDD
—
VDD
V
Input Low Voltage
PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD3, RESET,
IRQ, EXTAL
(TTL Level) VSYNC, HSYNC, SOG
SDA,SCL
VIL
VSS
—
0.2 x VDD
0.8
0.2 x VDD
V
Supply Current (see Notes)
Run
Wait
IDD
—
8
4
20
8
mA
I/O Ports Hi-Z Leakage Current
PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD3
IOZ
——
10
A
Input Current
RESET, IRQ, EXTAL, VSYNC, HSYNC
IIN
——
1
A
Capacitance
Ports (as Input or Output), RESET, IRQ, EXTAL, XTAL
HSYNC, VSYNC
COUT
CIN
—
12
8
pF
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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