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參數(shù)資料
| 型號： | MC68HC705BD7B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SDIP-42 |
| 文件頁數(shù)： | 58/85頁 |
| 文件大?。?/td> | 302K |
| 代理商： | MC68HC705BD7B |
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SECTION 10: SYNC PROCESSOR
MOTOROLA
Page 51
MC68HC05BD7 Rev. 2.0
GENERAL RELEASE SPECIFICATION
PRELIMINARY
10.3
Registers
There are five registers associated with the SYNC PROCESSOR module as described
below.
10.3.1
Sync Processor Control and Status Register (SPCSR)
NOTE:
Please don’t use BSET or BCLR to manipulate this register when VSIE is
set and I-bit is clear, or it will cuase abnormal reset.
VSIE
bit 7
When VSync Interrupt Enable (VSIE) bit is set, the VSIF flag
is enabled to generate an interrupt request to the CPU. When
VSIE is cleared, the VSIF flag is prevented from generating an
interrupt request. Reset clears this bit.
VEDGE
bit 6
The VEDGE bit specifies the triggering edge of VSYNC
interrupt. When it is zero, the rising edge of internal VSYNC
signal which is either from the VSYNC pin or extracted from
the composite input signal will set VSIF flag. When it is one,
the falling edge of internal VSYNC signal will set VSIF flag.
Reset clears this bit.
VSIF
bit 5
This flag is a read-only bit and is set by the specified edge of
internal VSYNC signal which is either from the VSYNC pin or
extracted from the composite input signal. The triggering
edge is specified by the VEDGE bit, see the above description
of VEDGE for details. It is cleared by writing a zero to it or
reset.
COMP
bit 4
This COMPosite video input enable bit is set to enable the
separator circuit which extracts the VSYNC pulse from
composite input in HSYNC pin. The extracted VSYNC pulse
will be fed into the vertical counter, vertical polarity detection
circuit, and VSYNO output circuit as well. Its measurable
timing is the same as the separate VSYNC pin input. Reset
clears this bit.
VINVO
bit 3
This bit controls the output polarity of the VSYNO signal.
When it is zero, the VSYNO output is identical to the VSYNC
input. When it is one, the inverted VSYNC signal is output to
VSYNO pin.
0
7
0000000
6543210
W
R
SPCSR
$000C
reset
VSIF
COMP
VEDGE
VSIE
VPOL
HPOL
HINVO
VINVO
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