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參數(shù)資料
| 型號： | MC68HC705BD7B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SDIP-42 |
| 文件頁數(shù)： | 59/85頁 |
| 文件大?。?/td> | 302K |
| 代理商： | MC68HC705BD7B |
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MOTOROLA
SECTION 10: SYNC PROCESSOR
Page 52
GENERAL RELEASE SPECIFICATION
MC68HC05BD7 Rev. 2.0
PRELIMINARY
HINVO
bit 2
This bit controls the output polarity of the HSYNO signal.
When it is zero, the HSYNO output is identical to the HSYNC
input. When it is one, the inverted HSYNC signal is output to
HSYNO pin.
VPOL
bit 1
This bit shows the polarity of VSYNC input. If it is one, the
VSYNC input has positive polarity. If it is zero, the VSYNC
input has negative polarity. Reset clears this bit.
HPOL
bit 0
This bit shows the polarity of HSYNC input. If it is one, the
HSYNC input has positive polarity. If it is zero, the HSYNC
input has negative polarity. Reset clears this bit.
10.3.2
Sync Processor Input/Output Control Register (SPIOCR)
VSYNCS
bit 7
The VSYNCS bit reflects the logical state of VSYNC input. It
is a read only bit.
HSYNCS
bit 6
The HSYNCS bit reflects the logical state of HSYNC input. It
is a read only bit.
COINV
bit 5
This Clamp Output INVert bit will invert the CLAMP output.
When it is zero, the CLAMP output has default positive going
pulse as illustrated in Figure 10-1. When it is one, the CLAMP
output is inverted as negative pulse generated. Reset clears
this bit.
HVTST
bit 4
This HV TeST bit is reserved for testing purpose. It can be
accessed only in test mode. So user must be careful while
developing the program in EVS platform. Reset clears this bit.
SOGIN
bit 3
If the SOGIN bit is one, the SOG pin which is shared with PD3
will be selected as the composite sync input when the COMP
bit in SPCSR register is one. If it is zero, the HSYNC pin is the
default composite input pin when the COMP bit is one. Reset
clears this bit.
CLAMPOE
bit 2
The CLAMP Output Enable bit is set to configure the PD2 pin
as the CLAMP pulse output pin. Reset clear this bit.
BPOR
bit 1
The Back PORch bit defines the triggering edge of clamp
output. When it is one, the clamp pulse is generated at the
trailing edge of HSYNC input. When it is zero, the clamp pulse
is generated at the leading edge of HSYNC input. Reset
clears this bit.
SOUT
bit 0
The SOUT will select the output signals of VSYNO and
HSYNO from the internal free-running counter. When it is
zero, the incoming HSYNC and VSYNC or extracted VSYNC
0
7
0000000
6543210
W
R
SPIOCR
$0011
reset
BPOR
SOUT
CLAMPOE
SOGIN
HVTST
COINV
HSYNCS
VSYNCS
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