參數(shù)資料
型號(hào)： MC68HC705BD7B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP42
封裝： SDIP-42
文件頁數(shù)： 10/85頁
文件大?。?/td> 302K
代理商： MC68HC705BD7B
MOTOROLA
SECTION 1: GENERAL DESCRIPTION
Page 8
GENERAL RELEASE SPECIFICATION
MC68HC05BD7 Rev. 2.0
PRELIMINARY
1.2.4
RESET
This active low input-only pin is used to reset the MCU to a known start-up state. The
RESET pin contains an internal Schmitt trigger as part of its input to improve noise
immunity. See SECTION 5 for more details.
1.2.5
PA0-PA7
These eight I/O lines comprise Port A. The state of any pin is software programmable and
all Port A lines are configured as inputs during Reset. See SECTION 7 for a detailed
description of I/O programming.
1.2.6
PB0-PB5
These six I/O lines comprise Port B. The state of any pin is software programmable and all
Port B lines are configured as inputs during Reset. PB2 to PB5 are +12V open-drain pins.
See SECTION 7 for a detailed description of I/O programming.
1.2.7
PC0*/PWM8*-PC1*/PWM9*
These two +12V open-drain pins are either 8-bit PWM channels 8 to 9 outputs or general
purpose I/O port C. The state of any pin is software programmable and all Port C lines are
configured as inputs during Reset. See SECTION 7 for a detailed description of I/O
programming.
1.2.8
PC2/PWM10/ADC0- PC5/PWM13/ADC3
These four pins can be selected as general purpose I/O of port C, PWM or ADC input
channel 0-2. See SECTION 7 for how to configure the pins. Also see SECTION 8 and
SECTION 12 for a detailed description of these modules.
1.2.9
PC6/PWM14/VSYNO, PC7/PWM15/HSYNO
These two pins can be selected as general purpose I/O of port C, PWM or sync signal
outputs. See SECTION 7 for how to configure the pins. Also see SECTION 8 and SECTION
10 for a detailed description of these modules.
1.2.10
PD0*/SDA*, PD1*/SCL*
These pins are either general purpose I/O pins of port D or the data line (SDA) and clock
line (SCL) of DDC12AB. These two pins are open-drain pins. See SECTION 7 for how to
configure the pins. See SECTION 9 for a detailed description.
1.2.11
PD2***/CLAMP, PD3*/SOG
The PD2*** is +5V open-drain general purpose I/O pin and the PD3* is +12V open-drain
general purpose I/O pin. The PD2 pin could become the CLAMP pulse push-pull output to
Pre-AMP IC and the PD3 pin could become the SOG digital input of the Sync Processor
when the corresponding enable bit in SPIOCR register is set. These two pins will not be
bonded out in 40-pin DIP package.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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