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參數(shù)資料
| 型號： | MC68HC705BD7B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SDIP-42 |
| 文件頁數(shù)： | 61/85頁 |
| 文件大?。?/td> | 302K |
| 代理商： | MC68HC705BD7B |
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MOTOROLA
SECTION 10: SYNC PROCESSOR
Page 54
GENERAL RELEASE SPECIFICATION
MC68HC05BD7 Rev. 2.0
PRELIMINARY
the VFRs registers are meaningless. The data corresponds to the period of one vertical
frame. This register can be read to determine if the frame frequency is valid, and to
determine the video mode. The MSB in the VFHR register will indicate the overflow
condition when the period of VSYNC frame exceeds 64.768ms (lower than 15.258Hz). This
VOF flag is default to be zero and will be update every vertical frame or set when the
counter overflows.
The frame frequency is calculated by 1/(VFR
±1 x 8S) or 1/(VFR±1 x 16 x tcyc).
The table above shows examples for the Vertical Frequency Register, all VFR numbers are
in hexadecimal:
10.3.4
Hsync Frequency Registers (HFRs)
This 13-bit read-only register pair contains the number of horizontal lines within 32ms and
one overflow bit, HOVER. An internal line counter counts the horizontal sync pulses within
32ms window of every 32.768ms period. The most significant 7 bits of counted value will
then be transferred to high byte register, $0F, and the least significant 5 bits of counted
value is transferred to one intermediate buffer. When the high byte register is read, the 5-
bit counted value stored in the intermediate buffer will be uploaded to the low byte register,
$10. So the program must read the high byte register first then low byte register in order to
get the complete counted value of horizontal pulses. The HOVER bit will be set immediately
if the number of incoming horizontal sync pulses in 32ms are more than 4095, that means
HSYNC frequency is over 128KHz. The HFHR data can be read to determine the number
of KHz of HSYNC frequency and the HFLR shows the sub-KHz value of HSYNC frequency.
This makes user easy to read the frequency of HSYNC and determine the video mode.
10.4
System Operation
This module is used mainly for user to determine the video mode of incoming HSYNC and
VSYNC of various frequency and polarity. It is designed to assist in determining the video
mode including DPMS modes. The definition of ’No pulses’ of DPMS standard can be
detected when the value of H counter register is less than one or the VOF in the VFHR
register is set. For the HSYNC counter value will be updated repeatedly every 32.768ms
0
7
0000000
6543210
W
R
HFHR
$000F
reset
HOVER
HFH6
HFH5
HFH4
HFH3
HFH2
HFH1
HFH0
0
7
0000000
6543210
W
R
HFLR
$0010
reset
0
HFL4
HFL3
HFL2
HFL1
HFL0
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