參數(shù)資料
型號(hào)： MC68HC705BD7B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP42
封裝： SDIP-42
文件頁(yè)數(shù)： 48/85頁(yè)
文件大?。?/td> 302K
代理商： MC68HC705BD7B
MOTOROLA
SECTION 9: DDC12AB INTERFACE
Page 42
GENERAL RELEASE SPECIFICATION
MC68HC05BD7 Rev. 2.0
PRELIMINARY
MAST
Bit 4
If the software set the MASTer control bit, the module will
generate a start condition to the SDA and SCL lines and send
out the calling address which is stored in the DADR register.
But if the ALIF flag is set when arbitration loss occurs on the
lines, the module will discard the master mode by clearing the
MAST bit and release both SDA and SCL lines immediately.
This bit can also be cleared by writing zero to it or when the
NAKIF is set. When the MAST bit is cleared either by NAKIF
set or by software, not by ALIF set, the module will generate
the stop condition to the lines after the current byte
transmission is done. Reset clears this bit.
MRW
Bit 3
This MRW bit will be transmitted out as the bit 0 of the calling
address when the module sets the MAST bit to enter the
master mode. It will also determine the transfer direction of
the following data bytes. When it is one, the module is in
master receive mode. When it is zero, the module is in master
transmit mode. Reset clears this bit.
BR2-BR0
Bit 2-Bit 0
The three Baud Rate select bits will select one of eight clock
rates as the master clock when the module is in master mode.
The serial clock frequency is equal to the CPU clock divided
by the divider shown in following table. For the CPU clock will
be halted while program executes the WAIT instruction,
program must not enter WAIT mode when the DDC12AB
module is in Master mode in order not to hang up the
communication on the lines. These bits are cleared upon
reset.
Table 9-1: Pre-scaler of Master Clock Baudrate
BR2:BR1:BR0
DIVIDER
0 : 0 : 0
0 : 0 : 1
0 : 1 : 0
0 : 1 : 1
1 : 0 : 0
1 : 0 : 1
1 : 1 : 0
1 : 1 : 1
20
40
80
160
320
640
1280
2560
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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