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參數(shù)資料
| 型號： | MC68HC05CL48 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.802 MHz, MICROCONTROLLER, PQFP112 |
| 封裝： | TQFP-112 |
| 文件頁數(shù)： | 81/145頁 |
| 文件大?。?/td> | 673K |
| 代理商： | MC68HC05CL48 |
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GENERAL RELEASE SPECIFICATION
June 11, 1997
MOTOROLA
INTERRUPTS
MC68HC05CL48
4-8
REV 2.0
4.3.2.4
External Interrupt Status Register (EXISR)
KBIF[7:3]
The keyboard interrupt flag bit is set to ‘1’ when a negative edge has been
detected at the pin and the corresponding enable bit has been set. Writing a ‘0’
to this bit will clear the corresponding interrupt flag. This bit should be cleared
by software in the keyboard interrupt service routine, or the CPU will keep on
serving this interrupt.
IRQF[2:0]
The external IRQ flag bit is set to ‘1’ when an appropriate edge has been
detected at the pin and the corresponding enable bit has been set. Writing a “0”
to this bit will clear the IRQ interrupt flag. This bit should be cleared by software
in the keyboard interrupt service routine, or the CPU will keep on serving this
interrupt.
4.3.3 Caller ID Interrupt (RDI/CDI,CDRI)
This interrupt is caused by the Caller ID module when a valid RT_L signal, a Ring
is detected, a Carrier is detected or when the 8-bit Called ID data is ready to be
read. The enable and ag bits for the Ring Detect and the Carrier detect are
located in CLCSR1 register and the enable and ag bits for the Called ID data
ready are located in CLCSR3 register. The RT_L is always active once it is
enabled by a metal mask, see Section 11. All four interrupts will vector to the
same interrupt service routine located at the addresses specied by the contents
of memory locations $FFF4-$FFF5. The RT_L interrupt will wake up the MCU
from the STOP and WAIT mode whereas the Ring Detect, Carrier Detect and
Data Ready interrupts will wake up the CPU from Wait mode. See Section 6.
4.3.4 TIMER Interrupt
The TIMER interrupt is generated by the multi-function Timer when a timer
overow or an input capture or a output compare has occurred as described in
Section 8. The interrupt enable bit and ag for the Timer interrupt are located in
the Timer Control and Status Registers TCR and TSR located at $0011 and $0012
respectively. The I-bit in the CCR must be clear in order for the Timer interrupt to
76543210
EXISR
$001E
READ
KBIF7
KBIF6
KBIF5
KBIF4
KBIF3
IRQF2
IRQF1
IRQF0
WRITE
RESET
00000000
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