參數(shù)資料
型號(hào)： MC68HC05CL48
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 1.802 MHz, MICROCONTROLLER, PQFP112
封裝： TQFP-112
文件頁(yè)數(shù)： 10/145頁(yè)
文件大?。?/td> 673K
代理商： MC68HC05CL48
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June 11, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05CL48
PHASE-LOCKED LOOP
MOTOROLA
REV 2.0
13-1
SECTION 13
PHASE-LOCKED LOOP
System clock can be obtained either from the external 32kHz oscillator or from the
PLL. During power on or external reset, the system is defaulted to use the 32 kHz
clock from the external oscillator. This is to prevent the system from using
otherwise, an unstable clock from the PLL during reset. To use the PLL clock after
power on or external reset, the PON-bit should be set ‘1’ rst to switch the PLL on,
a minimum of 10msec should then be allowed for the PLL clock to stabilize before
setting the PCLK-bit to ‘1’ to switch to use the PLL clock. Power on or external
reset clears the PCLK-bit.
Four clocks at different frequencies are available to the system from the PLL using
the frequency select bits FREQ0 and FREQ1 of the PCSR, see Table 13-1.
The PLL can be powered down to save power by setting the PON-bit to ‘0’. When
the PLL is powered up after it has been powered down, again the system should
allow a minimum of 10msec before switching onto the PLL clock. The PLL when it
is powered up, will also provide the 1.8MHz clock for the Caller ID module. Before
switching the PLL off, the PCLK-bit must be cleared thus selecting the 32kHz
crystal clock as the system clock. A minimum of 2*OSC cycles should be allowed
for the system to switch from the PLL clock to the oscillator clock.
Table 13-1. System Clock Frequency Selection
FREQ1
FREQ0
System Clock
0
3.6MHz
0
1
1.8MHz
1
0
900kHz
1
450kHz
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