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| 型號(hào)： | MC68HC05CL48 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.802 MHz, MICROCONTROLLER, PQFP112 |
| 封裝： | TQFP-112 |
| 文件頁(yè)數(shù)： | 104/145頁(yè) |
| 文件大?。?/td> | 673K |
| 代理商： | MC68HC05CL48 |
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June 11, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05CL48
TIMER
MOTOROLA
REV 2.0
8-9
Two 8-bit registers, which make up the 16-bit input capture register, these are
read-only and are used to latch the value of the free-running counter after the
corresponding input capture edge detector senses a dened transition. The level
transition which triggers the counter transfer is dened by the corresponding input
edge bit (IEDG1). Reset does not affect the contents of the input capture register.
IEDG1 = 0: Capture on negative edge
IEDG1 = 1: Capture on positive edge
An interrupt can also accompany a capture provided the corresponding interrupt
enable bit, ICI1E (bit 7 of the timer control register $11) is set.
The result obtained by an input capture will be one more than the value of the
free-running counter on the rising edge of the internal bus clock preceding the
external transition. This delay is required for internal synchronization. Resolution
is one count of the free-running counter, which is four internal bus clock cycles.
The free-running counter contents are transferred to the input capture register on
each proper signal transition regardless of whether the input capture ag (IC1F) is
set or clear. The input capture register always contains the free-running counter
value that corresponds to the most recent input capture.
After a read of the input capture register ($13) MSB, the counter transfer is
inhibited until the LSB ($14) is also read. This characteristic causes the time used
in the input capture software routine and its interaction with the main program to
determine the minimum pulse period.
A read of the input capture register LSB ($14) does not inhibit the free-running
counter transfer since they occur on opposite edges of the internal bus clock.
76543210
IC1L
$0014
READ
IC1:7
IC1:6
IC1:5
IC1:4
IC1:3
IC1:2
IC1:1
IC1:0
WRITE
RESET
UUUUUUUU
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