參數(shù)資料
型號: MC68HC05CL48
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 1.802 MHz, MICROCONTROLLER, PQFP112
封裝: TQFP-112
文件頁數(shù): 115/145頁
文件大?。?/td> 673K
代理商: MC68HC05CL48
June 11, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05CL48
TIMER
MOTOROLA
REV 2.0
8-19
8.3
ONE SECOND WATCH TIMER
The 1 second Watch Timer is a 15-bit free running counter which runs off the
32kHz external clock directly and is therefore not affected by Stop Mode or Wait
Mode. The Watch Timer is used to generate interrupts at 1 second interval to
wake up the CPU when the I-bit in the CCR is cleared. See Figure 8-7. The Watch
Timer overow ag WTOF is set when the a transition from $7FFF to $0000
occurs and will cause an interrupt if the WTOIE-bit of the Watch Timer control and
status register (WTCSR $0023) is set to ‘1’. This ag is latched and should be
cleared by the Watch Timer interrupt service routine to prevent unwanted
interrupts. Writing a ‘0’ to the WTOF-bit or reset clears the WTOF-bit.
Power on or external reset has no effect on the free running counter and therefore
the counter state is unknown after reset. However, the Watch Timer can be reset
to a known state by writing a ‘1’ to the WTR-bit in the Watch Timer control and
status register. The WTOF ag is prevented from being set during software reset.
Reading the WTR-bit will always return a ‘0’.
The Watch Timer can be disabled by writing a ‘1’ to the WTOFF-bit of the Watch
Timer control and status register, the value of the Watch Timer is retained during
the off period.
Table 8-2. RTI and COP Rates 17.5kHz Bus Frequency
BUS FREQUENCY = 17.5 kHz
RT1:RT0
Div. Ratio
RTI Rate
COP Rate (RTIx7)
00
214
0.94 s
6.58 s
01
215
1.88 s
13.16 s
10
216
3.76 s
26.32 s
11
217
7.52 s
52.64 s
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