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| 型號(hào)： | MC68HC05CL48 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.802 MHz, MICROCONTROLLER, PQFP112 |
| 封裝： | TQFP-112 |
| 文件頁數(shù)： | 109/145頁 |
| 文件大小： | 673K |
| 代理商： | MC68HC05CL48 |
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GENERAL RELEASE SPECIFICATION
June 11, 1997
MOTOROLA
TIMER
MC68HC05CL48
8-14
REV 2.0
The counter alternate register at address $1B and $1C contains the same value
as the free-running counter (at address $19 and $1A); therefore, this alternate
register can be read at any time without affecting the timer overow ag in the
timer status register.
8.1.6 Timer Pin Conguration Register (TIMCONF)
The timer pin conguration register is a read/write register, this is used to control
PTC[6:7] pin function.
CONF7- Pin conguration 7
1 =
Congures PTC7 as timer input capture pin.
0 =
PTC7 used as normal I/O port pin.
CONF6- Pin conguration 6
1 =
Congures PTC6 as timer input capture pin.
0 =
PTC6 used as normal I/O port pin.
8.1.7 Operation During Low Power Mode
During the wait and stop modes, the timer stops and holds at its current state,
retaining all data, and resumes operation from this point when external interrupt
(IRQ), or internal interrupt is received.
8.2
CORE TIMER
The MC68HC05CL48 Core Timer (or Ctimer) for is a 15-stage multi-functional
ripple counter. The features include Timer Over Flow, Power-On Reset (POR),
Real Time Interrupt, and COP Watchdog Timer.
As seen in Figure 8-6, the Timer is driven by the internal bus clock divided by four
with a xed prescaler. This signal drives an 8-bit ripple counter. The value of this
8-bit ripple counter can be read by the CPU at any time by accessing the Ctimer
Counter Register (CTCR) at address $09. A timer overow function is
implemented on the last stage of this counter, giving a possible interrupt at the
rate of E/1024. One additional stages produce the POR function at E/2064. The
Timer Counter Bypass circuitry (available only in Test Mode) is at this point in the
76543210
TIMCONF
$0006
READ
CONF7
CONF6
WRITE
RESET
0
UUUUU
0
U = UNAFFECTED
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