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參數(shù)資料
| 型號： | MC68HC05CL48 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.802 MHz, MICROCONTROLLER, PQFP112 |
| 封裝： | TQFP-112 |
| 文件頁數(shù)： | 73/145頁 |
| 文件大?。?/td> | 673K |
| 代理商： | MC68HC05CL48 |
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June 11, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05CL48
INTERRUPTS
MOTOROLA
REV 2.0
4-1
SECTION 4
INTERRUPTS
Interrupts cause the processor to save register contents on the stack and to set
the interrupt mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware
interrupts do not cause the current instruction execution to be halted, but are
considered pending until the current instruction is complete.
If interrupts are not masked (I-bit in the CCR is clear) and the corresponding
interrupt enable bit is set the processor will proceed with interrupt processing.
Otherwise, the next instruction is fetched and executed. If an interrupt occurs the
processor completes the current instruction, then stacks the current CPU register
states, sets the I-bit to inhibit further interrupts, and nally checks the pending
hardware interrupts. If more than one interrupt is pending following the stacking
operation, the interrupt with the highest vector location shown in Table 4-1 will be
serviced rst. The SWI is executed the same as any other instruction, regardless
of the I-bit state.
When an interrupt is to be processed the CPU fetches the address of the
appropriate interrupt software service routine from the vector table at locations
$FFF0 thru $FFFF as dened in Table 4-1.
An RTI instruction is used to signify when the interrupt software service routine is
completed. The RTI instruction causes the register contents to be recovered from
the stack and normal processing to resume at the next instruction that was to be
executed when the interrupt took place. Figure 4-1 shows the sequence of events
that occur during interrupt processing.
Table 4-1. Vector Address for Interrupts and Reset
Interrupts
CPU Interrupt
Vector Addresses
Reset
RESET
$FFFE-$FFFF
Software
SWI
$FFFC-$FFFD
External Interrupt
IRQ
$FFFA-$FFFB
Timer
TCAP1,TCAP2,TCMP1,TCMP2
$FFF8-$FFF9
SPI
$FFF6-$FFF7
Caller ID
CDI, RDI, CDRI, RT_L
$FFF4-$FFF5
External Interrupt/Keyboard Interrupt
IRQ0, IRQ1, IRQ2, KBI[7:3]
$FFF2-$FFF3
Core Timer/Watch Timer
Ctimer, WTimer
$FFF0-$FFF1
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