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| 型號(hào)： | MC68HC05CL48 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.802 MHz, MICROCONTROLLER, PQFP112 |
| 封裝： | TQFP-112 |
| 文件頁(yè)數(shù)： | 76/145頁(yè) |
| 文件大?。?/td> | 673K |
| 代理商： | MC68HC05CL48 |
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GENERAL RELEASE SPECIFICATION
June 11, 1997
MOTOROLA
INTERRUPTS
MC68HC05CL48
4-4
REV 2.0
interrupt will occur as soon as the interrupt mask bit is cleared. The latch will be
cleared by RESET or cleared automatically during fetch of the EXTERNAL
Interrupt vectors. Therefore, one (and only one) external interrupt edge could be
latched during the interrupt mask bit is set.
The service routine address is specied by the contents of $FFFA and $FFFB.
Figure 4-2 shows both a block diagram and the two methods for the interrupt line
(IRQ) to the processor. The rst method is single pulses on the interrupt line
spaced far enough apart to be serviced. The minimum time between pulses is a
function of the number of cycles required to execute the interrupt service routine
plus 21 cycles. Once a pulse occurs, the next pulse should not occur until the
MCU software has exited the routine (an RTI occurs). The second conguration
shows several interrupt line “wire-ANDed” to perform the interrupts at the
processor. Thus, if after servicing one interrupt and the interrupt line remains low,
then the next interrupt is recognized.
NOTE
INTO is located at bit-1 of the Option Register at $001F, and is set
by reset. The Option Register can only be written once after reset.
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