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參數(shù)資料
| 型號： | MC68HC05CL48 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.802 MHz, MICROCONTROLLER, PQFP112 |
| 封裝： | TQFP-112 |
| 文件頁數(shù)： | 119/145頁 |
| 文件大?。?/td> | 673K |
| 代理商： | MC68HC05CL48 |
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June 11, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05CL48
SERIAL PERIPHERAL INTERFACE
MOTOROLA
REV 2.0
9-3
from the bus clock. The clock rate is selected by bits (SPR1,SPR0) in the control
register. The SCK pin on the Master device becomes a xed output providing the
system clock to an enabled Slave or Slaves. The clock is used by the Master to
latch incoming Slave data on the MISO pin and shift out data to the Slave device
on the MOSI pin. The Master and Slave must be operated in the same timing
mode. The type of clock and its’ relationship with the data is controlled by bits
CPOL and CPHA. Reference Figure 9-1.
9.1.4 SS SLAVE SELECT (INPUT)
9.1.4.1
Slave Mode
The slave select (SS input) is generated by the master (parallel port may be used)
and used to “enable one” of several slaves to accept and/or return data or “enable
several” slaves to accept data. To insure a data byte transfer, the SS signal must
be low prior to occurrence of SCK and must not become high until after the 8th
(last) SCK cycle. Figure 9-1 shows the clock (SCK) and data relationship.
Depending on the state of the CPHA control bit, the SS pin pulled low: (1) allows
the rst bit of data onto the MISO system line for transfer and (2) prevents the
Slave from reading or writing the data register. A further description of the affect of
the (SS) pin and (CPHA) control bit on the i/o data register is given in the
description of the (WCOL) status ag. The (WCOL) ag warns the Slave if it has
had a conict between a transmission and a write of the data register. A high level
on SS forces MISO to the hi-Z state. Also, SCK and MOSI are ignored by the
disabled slave.
9.1.4.2
Master Mode
In this mode, Slave Select (SS) input is monitored to assure that it stays false
(high). If Slave Select becomes true, the device immediately exits the master
mode and becomes a slave (MSTR=0). Also, control bit (SPE) is forced to a zero
causing all SPI system pins to be inputs. An interrupt ag (MODF) is set warning
the device that the above events have occurred. The signicance of this is that a
collision has occurred; that is, two devices have both become masters. This is
normally the result of software error, although some systems may allow the
default master to “knock all other masters off the bus” if an erroneous bus state is
detected. This is, of course, a catastrophic event and it is the responsibility of the
default master to completely “clean up” the system.
9.2
SPI REGISTERS
The register addresses only show the low order address bits i.e ABL(1:0). The
registers can be placed anywhere in the device memory map by generating an
appropriate ‘Module Select’ signal in the map logic.
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