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參數(shù)資料
| 型號(hào)： | MC68HC05BD7P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 65/85頁 |
| 文件大?。?/td> | 302K |
| 代理商： | MC68HC05BD7P |
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MOTOROLA
SECTION 11: MULTI-FUNCTION TIMER
Page 58
GENERAL RELEASE SPECIFICATION
MC68HC05BD7 Rev. 2.0
PRELIMINARY
$FF to $00. A CPU interrupt request will be generated if
TOFIE is set. TOF is a clearable, read-only status bit. Clearing
the TOF is done by writing a ’0’ to TOF.
RTIF
bit 6
Real Time Interrupt Flag indicates if the output of the RTI
circuit goes active. The clock frequency that drives the RTI
circuit is E/2,048, giving a maximum interrupt period of 1.024
milliseconds at a bus rate of 2 MHz. A CPU interrupt request
will be generated if RTIE is set. RTIF is a clearable, read-only
status bit. Clearing the RTIF is done by writing a ’0’ to RTIF.
TOFIE
bit 5
When Timer Over Flow Interrupt Enable (TOFIE) bit is set, the
TOF flag is enabled to generate an interrupt request to the
CPU. When TOFIE is cleared, the TOF flag is prevented from
generating an interrupt request.
RTIE
bit 4
When Real Time Interrupt Enable (RTIE) is set, the RTIF flag
is enabled to generate an interrupt request to the CPU. When
RTIE is cleared, the RTIF flag is prevented from generating an
interrupt request.
IRQN
bit 3
0 = Both level and edge triggering are detected for external
interrupt (IRQ).
1 = Only edge triggering is detected for external interrupt.
INHIRQ
bit 2
The INHibit IRQ bit will inhibit the external interrupt input.
When it is set, no active falling edge or low period will be
recognized as interrupt request. It is possible for a low state
input on the IRQ pin to be seen as a falling edge event when
the INHIRQ bit changes from one to zero, see Figure 4-2 for
reference. Reset clears this bit.
RT1-0
bit 1,0
These two bits are used to define real time interrupt rate as
well as COP reset rate as tabulated in Table 11-1. Reset sets
these two bits for the slowest watchdog reset rate. Note that
the minimal COP reset period is determined by dividing the
COP master clock, which is the real time interrupt clock, by
63(63=64-1). The reason is that COP reset operation is
asynchronous to COP master clock edge. Therefore it is
possible that right after COP reset operation, a COP master
clock edge arrives to start counting COP period. The effective
count of the divide-by-64 counter is hence 63 rather than 64.
RT1, RT0 should only be changed right after COP timer has
been reset; otherwise, unpredictable result will occur.
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