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參數(shù)資料
| 型號： | MC68HC05BD7P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 44/85頁 |
| 文件大小： | 302K |
| 代理商： | MC68HC05BD7P |
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SECTION 9: DDC12AB INTERFACE
MOTOROLA
Page 39
MC68HC05BD7 Rev. 2.0
GENERAL RELEASE SPECIFICATION
PRELIMINARY
SECTION 9
DDC12AB INTERFACE
9.1
Introduction
This DDC12AB Interface Module is mainly used for monitor to show its identification
information to video controller. It contains DDC1 hardware and a two-wire, bidirectional
serial bus which is fully compatible with multi-master IIC bus protocol to support DDC2AB
interface. In DDC1 type of communication, the module is in transmit mode. For DDC2AB
protocol, the module can be either in transmit mode or in receive mode upon host’s
commands. When DDC1 hardware is enabled, the loaded data is serially clocked out to
SDA line by the rising edge of VSYNC input signal continuously. If DDC2 protocol is
selected, the module will act as a standard IIC module, and will response only when it is
addressed or in master mode. During DDC1 communication, the falling transition in the
SCL line can be detected to interrupt cpu for mode switching.
This module not only can be applied in DDC12AB communication, but also can be used as
one typical command reception serial bus for factory setup and alignment purpose. It also
provides the flexibility of hooking additional devices to an existing system in future
expansion without adding extra hardware.
This DDC12AB module uses the SCL clock line and the SDA data line to communicate with
external DDC host or IIC interface. These two pins are shared with PD0 and PD1 port pins.
The outputs of SDA and SCL pins are all open-drain type. It means no clamping diode
connected between the pin and internal VDD. The maximum data rate typically is 100K bps.
The maximum communication length and the number of devices that can be connected are
limited by a maximum bus capacitance of 400 pF.
9.2
DDC12AB Features
DDC1 hardware
Fully compatible with multi-master IIC Bus standard
Software controllable acknowledge bit generation
Interrupt driven byte by byte data transfer
Calling address identification interrupt
Auto detection of RW bit and switching of transmit or receive mode
accordingly
Detection of START, repeated START, and STOP signals
Auto generation of START and STOP condition in master mode
Arbitration loss detection and No-ACK awareness in master mode
Master clock generator with 8 selectable baud rates
Automatic recognition of the received acknowledge bit
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