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參數資料
| 型號： | MC68HC05BD7P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數： | 64/85頁 |
| 文件大?。?/td> | 302K |
| 代理商： | MC68HC05BD7P |
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SECTION 11: MULTI-FUNCTION TIMER
MOTOROLA
Page 57
MC68HC05BD7 Rev. 2.0
GENERAL RELEASE SPECIFICATION
PRELIMINARY
SECTION 11
MULTI-FUNCTION TIMER
11.1
Introduction
This module provides miscellaneous function to the MC68HC05BD7. It includes a timer
overflow, real-time interrupt, and watchdog functions. Also included in the module is the
capability of selecting the mode of the maskable external interrupt pin, either edge-
triggered mode only or both edge-triggered mode and level-triggered mode.
The clock base for this module is derived from bus clock divided by four. For a 2 MHz E
(CPU) clock, the clock base is 0.5 MHz. This clock base is then divided by an 8-stage ripple
counter to generate the timer overflow. Timer overflow rate is thus E/1024. The output of
this 8-stage ripple counter then drives one stage divider to generate real time interrupt.
Hence, the clock base for real time interrupt is E/2,048. Real time interrupt rate is selected
by RT0 and RT1 bits of Multi-Function Timer Control/Status Register (MFTCSR). The
interrupt rates are E/2,048, E/(2,048X2), E/(2,048X4), and E/(2,048X8). The selected real
time interrupt rate is then divided by 64 to generate COP reset.
The COP watchdog timer function is implemented by using a COP counter. The minimum
COP reset rates are controlled by RT0 and RT1 of MFTCSR. If the COP circuit times out,
an internal reset is generated and the normal reset vector is fetched. Preventing a COP
time-out is done by writing a ‘0’ to bit 0 of address $3FF0. This write operation resets the
divide-by-64 counter stage described in the previous paragraph. The COP counter has to
be cleared periodically by software with a period less than COP reset rate. It continues to
count even though the CPU is in WAIT mode. In MC68HC05BD7, the COP is always
enabled.
11.2
Register
There are two registers in the Multi-Function Timer as discussed below.
11.2.1
Multi-function Timer Control/status Register
NOTE:
Please don’t use BSET or BCLR to manipulate this register when I-bit is
clear, or it will generate abnormal reset.
TOF
bit 7
Timer Overflow Flag indicates if the 8-bit ripple counter
overflows. TOF is set when the 8-bit counter rolls over from
0
7
0000011
6543210
W
R
MFTCSR
$0008
reset
TOF
RTIF
TOFIE
RTIE
IRQN
RT1
RT0
INHIRQ
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