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參數(shù)資料
| 型號： | MC68HC05BD7P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 28/85頁 |
| 文件大?。?/td> | 302K |
| 代理商： | MC68HC05BD7P |
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MOTOROLA
SECTION 4: INTERRUPTS
Page 24
GENERAL RELEASE SPECIFICATION
MC68HC05BD7 Rev. 2.0
PRELIMINARY
the interrupt service routine plus 21 cycles. Once a pulse occurs, the next pulse should not
occur until the MCU software has exited the routine (an RTI occurs). The second
configuration shows several interrupt line “wire-ANDed” to perform the interrupts at the
processor. Thus, if after servicing one interrupt and the interrupt line remains low, then the
next interrupt is recognized.
NOTE:
IRQN is located at bit 3 of the Multi-function Timer Register at $0008, and
is cleared by reset.
Figure 4-2: External Interrupt
4.4.2
VSYNC Interrupt
The VSYNC interrupt is generated when a specific edge of VSYNC input is detected as
described in SECTION 10. The interrupt enable bit, VSIE, for the VSYNC interrupt is
located at bit 7 of SYNC Processor Control and Status Register (SPCSR) at $000C. The I-
bit in the CCR must be cleared in order for the VSYNC interrupt to be enabled. This
interrupt will vector to the interrupt service routine located at the address specified by the
contents of $3FF8 and $3FF9. The VSYNC Interrupt Flag (VSIF) must be cleared by writing
’0’ to it in the interrupt routine.
4.4.3
DDC12AB Interrupt
The DDC12AB interrupt is generated by the DDC12AB circuit as described in SECTION 9.
The interrupt enable bit for the DDC12AB interrupt is located at bit 6 of DDC12AB Control
Register (DCR) at $0018. The I-bit in the CCR must be cleared in order for the DDC12AB
interrupt to be enabled. This interrupt will vector to the interrupt service routine located at
the address specified by the contents of $3FF6 and $3FF7.
IRQ
IRQ1
IRQn
IRQ
(MCU)
tILIH
tILIL
tILIH
Edge-sensitive Trigger Condition
The minimum pulse width tILIH is one
The period tILIL should not be less than the
number of cycles it takes to execute the
interrupt service routine plus 21 cycles
Level-sensitive Trigger Condition
If after servicing an interrupt, the IRQ
Normally used with pull-up resistor for
remains low, then the next interrupt is
recognized.
Wire-Ored connection
internal bus period.
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