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參數(shù)資料
| 型號： | MC68HC05BD7P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 47/85頁 |
| 文件大?。?/td> | 302K |
| 代理商： | MC68HC05BD7P |
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SECTION 9: DDC12AB INTERFACE
MOTOROLA
Page 41
MC68HC05BD7 Rev. 2.0
GENERAL RELEASE SPECIFICATION
PRELIMINARY
TXAK
Bit 3
If the transmit acknowledge enable bit (TXAK) is cleared, an
acknowledge signal will be sent out to the bus at the 9th clock
bit after receiving 8 data bits. When TXAK is set, no
acknowledge signal will be generated at the 9th clock (i.e.,
acknowledge bit = 1). Reset clears this bit.
SCLIEN
Bit 2
If the SCL Interrupt ENable bit (SCLIEN) is set, the interrupt
occurs provided the SCLIF in the status register is set and the
I-bit in the Condition Code Register is cleared. If SCLIEN is
cleared, the interrupt of SCLIF is disabled. Reset clears this
bit.
DDC1EN
Bit 1
When DDC1 protocol ENable (DDC1EN) is set, the VSYNC
input will be selected as clock input of DDC module. Its rising
edge will continuously clock out the data in the shift register.
No calling address comparison is performed. The RW bit in
the status register will be fixed to be one. If this bit is clear, the
SCLIF bit in the status register is also cleared. Reset clears
this bit.
9.3.3
DDC Master Control Register (DMCR)
The DMCR contains two interrupt flags, one bus status flag, two master mode control bits,
and three baudrate select bits.
ALIF
Bit 7
The Arbitration Loss Interrupt Flag is set when software
attempt to set MAST but the BB has been set by detecting the
start condition on the lines or when the DDC12AB module is
transmitting a ’one’ to SDA line but detected a ’zero’ from SDA
line in master mode, which is so called arbitration loss. This
bit can generate an interrupt request to cpu when the DIEN bit
in DCR register is set and I-bit in the Condition Code Register
is clear. This bit is cleared by writing ’0’ to it or by reset.
NAKIF
Bit 6
The No AcKnowledge Interrupt Flag is only set in master
mode when there is no acknowledge bit detected after one
data byte or calling address is transferred. This bit can
generate an interrupt request to cpu when the DIEN bit in
DCR register is set and I-bit in the Condition Code Register is
clear. This bit is cleared by writing ’0’ to it or by reset.
BB
Bit 5
The Bus Busy Flag is set after a start condition is detected,
and is reset when a stop condition is detected. This bit can
supplement the software in initiating the master mode
protocol. Reset clears this bit.
0
7
0000000
6543210
W
R
DMCR
$0016
reset
MRW
ALIF
NAKIF
BR2
BR1
BB
MAST
BR0
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