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參數(shù)資料
| 型號： | MC68HC05BD7P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 46/85頁 |
| 文件大?。?/td> | 302K |
| 代理商： | MC68HC05BD7P |
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MOTOROLA
SECTION 9: DDC12AB INTERFACE
Page 40
GENERAL RELEASE SPECIFICATION
MC68HC05BD7 Rev. 2.0
PRELIMINARY
9.3
Registers
There are six different registers used in the DDC12AB module and the internal
configuration of these registers is discussed in the following paragraphs.
9.3.1
DDC Address Register (DADR)
DAD7-DAD1 Bit 7-Bit 1
These 7 bits can be the DDC2 interface’s own specific slave
address in slave mode or the calling address when in master
mode. So the program must update it as the calling address
while entering the master mode and restore its own slave
address after the master mode is quitted. This register is
cleared as $A0 upon reset.
EXTAD
Bit 0
The EXTAD bit is set to expand the calling address of this
module. When it is one, the module will acknowledge the
general call address $00 and the address comparison circuit
will only compare the 4 MSB bits in the DADR register. For
example, the DADR contains $A1, that means EXTAD is
enabled and the calling address is $A0, therefore, the module
can acknowledge the calling address of $00 and $A0 to $AF.
When it is clear, the module will only acknowledge to the
specific address which is stored in the DADR register. It is
clear upon reset.
9.3.2
DDC Control Register (DCR)
The DCR provides five control bits. DCR is cleared upon reset.
DEN
Bit 7
If the DDC module ENable bit (DEN) is set, the DDC module
is enabled. If the DEN is clear, the interface is disabled and all
flags will restore its power-on default states. Reset clears this
bit.
DIEN
Bit 6
If the DDC Interrupt ENable bit (DIEN) is set, the interrupt
occurs provided the TXIF or RXIF in the status register is set
or the ALIF or NAKIF in the DMCR register is set and the I-bit
in the Condition Code Register is cleared. If DIEN is cleared,
the interrupt of TXIF, RXIF, ALIF, and NAKIF are all disabled.
Reset clears this bit.
DAD7
1
7
DAD1
0100000
6543210
DAD4
W
R
DADR
$0017
reset
DAD5
DAD6
DAD2
DAD3
EXTAD
0
7
0X
X0
0
X
6543210
W
R
DCR
$0018
reset
TXAK
DEN
DIEN
SCLIEN
DDC1EN
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