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參數資料
| 型號： | MC68HC05BD7P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數： | 38/85頁 |
| 文件大小： | 302K |
| 代理商： | MC68HC05BD7P |
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SECTION 7: INPUT/OUTPUT PORTS
MOTOROLA
Page 33
MC68HC05BD7 Rev. 2.0
GENERAL RELEASE SPECIFICATION
PRELIMINARY
SECTION 7
INPUT/OUTPUT PORTS
In the User Mode there are 26 bidirectional I/O lines arranged as 4 I/O ports (Port A, B, C,
and D). The individual bits in these ports are programmable as either inputs or outputs
under software control by the data direction registers (DDRs). Also, if enabled by software,
Port C and D will have additional functions as PWM outputs, DDC I/O and Sync Signal
Processor outputs.
7.1
Port A
Port A is an 8-bit bidirectional port which does not share any of its pins with other
subsystems. The Port A data register is at $00 and the data direction register (DDR) is at
$04. Reset does not affect the data register, yet clears the data direction register, thereby
returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to
output mode.
7.2
Port B
Port B is a 6-bit bidirectional port which does not share any of its pins with other
subsystems. PB2 to PB5 are +12V open-drain port pins. The Port B data register is at $01
and the data direction register (DDR) is at $05. Reset does not affect the data register, yet
clears the data direction register, thereby returning the ports to inputs. Writing a one to a
DDR bit sets the corresponding port bit to output mode.
7.3
Port C
Port C is an 8-bit bidirectional port which shares pins with PWM, Sync Processor, and ADC
subsystem. See SECTION 8 for a detailed description of PWM, SECTION 10 for a detailed
description of SYNC Processor, and SECTION 12 for a detailed description of ADC. These
pins are configured as PWM outputs when the corresponding bits in the CONFIGURATION
REGISTER 1 are set. PC6 and PC7 are configured to VSYNO and HSYNO outputs when
the corresponding bits in the CONFIGURATION REGISTER 2 are set. And PC2 to PC5 are
configured as ADC input channels as the corresponding bit in the CONFIGURATION
REGISTER 2 are set. If there is any confliction between the two configuration registers, the
CONFIGURATION REGISTER 2 has higher priority. The Port C data register is at $02 and
the data direction register (DDR) is at $06. Reset does not affect the data register, but
clears the data direction register, thereby returning the ports to inputs. Writing a one to a
DDR bit sets the corresponding port to output mode.
7.4
Port D
Port D is a 4-bit bidirectional port. PD0 and PD1 shares their pins with DDC12AB
subsystem. See SECTION 9 for a detailed description of DDC12AB. These two pins are
configured to the corresponding functions when the corresponding bits in the
CONFIGURATION REGISTER 2 are set. They have open-drain output and hysteresis
input level to improve noise immunity. PD2 is a +5V open-drain general I/O pin which
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