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參數(shù)資料
| 型號： | MC68EN302PV25BT |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-144 |
| 文件頁數(shù)： | 78/128頁 |
| 文件大?。?/td> | 641K |
| 代理商： | MC68EN302PV25BT |
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ETHERNET Controller
4-14
MC68EN302 REFERENCE MANUAL
MOTOROLA
E—Empty, written by Ethernet controller (=0) and user (=1).
0 = The data buffer associated with this BD has been filled with received data. A
receive buffer descriptor also has the E bit set to 0 when data reception has been
aborted due to an error condition. When E is set to 0, the status, length, reason and
AR Index fields are updated according to the event that just occured during
reception.
1 = The data buffer associated with this BD is empty, or reception is currently in
progress.
RO—Receive Buffer Software Ownership, written by user.
This bit is provided as a software ownership bit, if needed. Hardware does not alter the value
of this bit.
W—Wrap (Final BD in Table), written by user.
0 = This is not the last buffer descriptor in the Rx BD table.
1 = This is the last buffer descriptor in the Rx BD table. After this buffer has been used,
the Ethernet controller receives incoming data into the first BD in the table, allowing
the user to use fewer buffer descriptors than the number programmed by BDSIZE.
I—Interrupt, written by user.
0 = No interrupt is generated after this buffer has been filled.
1 = The RBINT bit in the interrupt event register is set when this buffer has been
completely filled by the Ethernet controller, indicating that the internal 68000 core
is free to process the buffer.
L—Last in Frame, written by Ethernet controller.
0 = The buffer is not the last in a frame.
1 = The buffer is the last in a frame.
F—First in Frame, written by Ethernet controller.
0 = The buffer is not the first in a frame.
1 = The buffer is the first in a frame.
M—Miss, written by Ethernet controller.
This bit is set by the Ethernet controller when the incoming frame is not matched by the
internal address recognition but is accepted because the Ethernet controller is operating in
promiscuous mode (PROM=1). The user can monitor the M-bit to quickly determine whether
the incoming frame was destined to this station. This bit is valid only if the L-bit is set. The
M-bit is valid even if INDEX_EN is not set.
0 = An address match in the CAM or hash algorithm caused frame reception.
1 = No address match occured on the received frame - promiscuous mode operation
caused frame reception.
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| MC68EN360AI25VL | 功能描述:微處理器 - MPU QUICC ETHRN RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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