參數(shù)資料
型號： MC68EN302PV25BT
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-144
文件頁數(shù)： 100/128頁
文件大?。?/td> 641K
代理商： MC68EN302PV25BT
Signal Descriptions
5-6
MC68EN302 REFERENCE MANUAL
MOTOROLA
5.3.2 IAC
This MC68302 output is not available on the MC68EN302 in the 144-pin TQFP package. It
is available in the PGA package.
5.3.3 BCLR
This MC68302 signal is not available on the MC68EN302. The additional EN302 logic
monitors the BCLR signal from the 302 core, but does not drive it.
5.3.4 FRZ
This MC68302 input is now pulled up internally and is not available on the MC68EN302 in
the 144 pin TQFP package. It is available in the PGA package.
5.3.5 BUSW
The BUSW signal (bus width) is a dedicated pin on the MC68302, but is muxed with
PARITY1 on the MC68EN302. This pin functions as BUSW only during system reset. If the
BUSW signal is low during EN302 reset, the EN8 bits in the CSER3–CSER0 register are
set. The BUSW signal is not passed to the 302 core on the MC68EN302, since the 302 core
of the MC68EN302 always operates in 16-bit mode. In 8-bit mode, bits D15–D8 of the data
bus are used. This is in contrast with the MC68302, which uses bits D7–D0 in 8-bit mode.
5.3.6 DISCPU
The DISCPU signal is a dedicated pin on the MC68302 but is muxed with PARITY0 on the
MC68EN302. This pin is DISCPU only during system reset.
5.4 MC68EN302 NEW SIGNALS MUXED WITH EXISTING MC68302
SIGNALS
Several pins on the MC68EN302 have enhanced MC68302 functionality. The additional
signal capability is controlled by the PM9–PM0 field in the MBCTRL (Module Bus Control)
register.
Table 5-2. Pin Muxing Control
PM[I]
MC68EN302
PM[I]=0
MC68EN302
PM[I]=1
MC68302
0
AMUX
BRG1
1
RAS0
BRG2/SDS2/PA7
2
RAS1
BRG3/PA12
3
CAS0
PB0/IACK7
4
CAS1
PB1/IACK6
5
DRAMRW
PB2/IACK1
6
A0
TOUT1/PB4
7
DREQ/PA13
WEL
DREQ/PA13
8
DACK/PA14
WEH
DACK/PA14
9OE
DONE/PA15
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