
56F8355 Description
56F8355 Technical Data
5
Preliminary
Optional on-chip regulator
FlexCAN (CAN Version 2.0 B-compliant) module with 2-pin port for transmit and receive
Two Serial Communication Interfaces (SCIs) each with two pins (or four additional GPIO lines)
Two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional GPIO
lines); SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B
Computer Operating Properly (COP) / Watchdog timer
Two dedicated external interrupt pins
49 General Purpose I/O (GPIO) pins; 21 pins dedicated to GPIO
External reset input pin for hardware reset
External reset output pin for system reset
Integrated low0voltage interrupt module
JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent,
real-time debugging
Software-programmable, Phase Lock Loop (PLL)-based frequency synthesizer for the core clock
1.1.4
Energy Information
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be
disabled
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
ADC smart power management
Each peripheral can be individually disabled to save power
1.2 56F8355 Description
The 56F8355 is a member of the 56800E core-based family of hybrid controllers. It combines, on
a single chip, the processing power of a DSP and the functionality of a microcontroller with a
flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the 56F8355 is well-suited for many
applications. The 56F8355 includes many peripherals that are especially useful for motion control,
smart appliances, steppers, encoders, tachometers, limit switches, power supply and control,
automotive control, engine management, noise suppression, remote utility metering, industrial
control for power, lighting, and automation applications.
The 56800E core is based on a Harvard-style architecture consisting of three execution units
operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style
programming model and optimized instruction set allow straightforward generation of efficient,
compact DSP and control code. The instruction set is also highly efficient for C/C++ Compilers to
enable rapid development of optimized control applications.
The 56F8355 supports program execution from internal or external memories. Two data operands
can be accessed from the on-chip data RAM per instruction cycle. The 56F8355 also provides two
external dedicated interrupt lines and up to 49 General Purpose Input/Output (GPIO) lines,
depending on peripheral configuration.