參數(shù)資料
型號: MC56F8355MFG60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 4-BIT, 120 MHz, OTHER DSP, PQFP128
封裝: LQFP-128
文件頁數(shù): 104/152頁
文件大?。?/td> 2224K
代理商: MC56F8355MFG60
Peripheral Memory Mapped Registers
56F8355 Technical Data
55
Preliminary
Table 4-26 Serial Peripheral Interface 1 Registers Address Map
(SPI1_BASE = $00 F2B0)
Register Acronym
Address Offset
Register Description
SPI1_SPSCR
$0
Status and Control Register
SPI1_SPDSR
$1
Data Size Register
SPI1_SPDRR
$2
Data Receive Register
SPI1_SPDTR
$3
Data Transmitter Register
Table 4-27 Computer Operating Properly Registers Address Map
(COP_BASE = $00 F2C0)
Register Acronym
Address Offset
Register Description
COPCTL
$0
Control Register
COPTO
$1
Time Out Register
COPCTR
$2
Counter Register
Table 4-28 Clock Generation Module Registers Address Map
(CLKGEN_BASE = $00 F2D0)
Register Acronym
Address Offset
Register Description
PLLCR
$0
Control Register
PLLDB
$1
Divide-By Register
PLLSR
$2
Status Register
Reserved
SHUTDOWN
$4
Shutdown Register
OSCTL
$5
Oscillator Control Register
Table 4-29 GPIOA Registers Address Map
(GPIOA_BASE = $00 F2E0)
Register Acronym
Address Offset
Register Description
Reset Value
GPIOA_PUR
$0
Pull-up Enable Register
0 x 3FFF
GPIOA_DR
$1
Data Register
0 x 0000
GPIOA_DDR
$2
Data Direction Register
0 x 0000
GPIOA_PER
$3
Peripheral Enable Register
0 x 3FFF
GPIOA_IAR
$4
Interrupt Assert Register
0 x 0000
GPIOA_IENR
$5
Interrupt Enable Register
0 x 0000
GPIOA_IPOLR
$6
Interrupt Polarity Register
0 x 0000
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