參數(shù)資料
型號: MC56F8355MFG60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 4-BIT, 120 MHz, OTHER DSP, PQFP128
封裝: LQFP-128
文件頁數(shù): 100/152頁
文件大小: 2224K
代理商: MC56F8355MFG60
Peripheral Memory Mapped Registers
56F8355 Technical Data
51
Preliminary
FIVAH1
$10
Fast Interrupt Vector Address High 1 Register
IRQP 0
$11
IRQ Pending Register 0
IRQP 1
$12
IRQ Pending Register 1
IRQP 2
$13
IRQ Pending Register 2
IRQP 3
$14
IRQ Pending Register 3
IRQP 4
$15
IRQ Pending Register 4
IRQP 5
$16
IRQ Pending Register 5
Reserved
ICTL
$1D
Interrupt Control Register
Table 4-20 Analog-to-Digital Converter Registers Address Map
(ADCA_BASE = $00 F200)
Register Acronym
Address Offset
Register Description
ADCA_CR 1
$0
Control Register 1
ADCA_CR 2
$1
Control Register 2
ADCA_ZCC
$2
Zero Crossing Control Register
ADCA_LST 1
$3
Channel List Register 1
ADCA_LST 2
$4
Channel List Register 2
ADCA_SDIS
$5
Sample Disable Register
ADCA_STAT
$6
Status Register
ADCA_LSTAT
$7
Limit Status Register
ADCA_ZCSTAT
$8
Zero Crossing Status Register
ADCA_RSLT 0
$9
Result Register 0
ADCA_RSLT 1
$A
Result Register 1
ADCA_RSLT 2
$B
Result Register 2
ADCA_RSLT 3
$C
Result Register 3
ADCA_RSLT 4
$D
Result Register 4
ADCA_RSLT 5
$E
Result Register 5
ADCA_RSLT 6
$F
Result Register 6
ADCA_RSLT 7
$10
Result Register 7
ADCA_LLMT 0
$11
Low Limit Register 0
ADCA_LLMT 1
$12
Low Limit Register 1
ADCA_LLMT 2
$13
Low Limit Register 2
ADCA_LLMT 3
$14
Low Limit Register 3
Table 4-19 Interrupt Control Registers Address Map
(ITCN_BASE = $00 F1A0) (Continued)
Register Acronym
Address Offset
Register Description
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參數(shù)描述
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