參數(shù)資料
型號: MC56F8355MFG60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 4-BIT, 120 MHz, OTHER DSP, PQFP128
封裝: LQFP-128
文件頁數(shù): 46/152頁
文件大?。?/td> 2224K
代理商: MC56F8355MFG60
14
56F8355 Technical Data
Preliminary
2.2 56F8355 Signal Pins
After reset, all pins are by default the primary function. Any alternate functionality must be
programmed.
EMI is not functional in this package; since only part of the address/data bus is bonded out, use as
GPIO pins.
If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state.
Other states show the reset condition of the alternate function, which you get if the alternate pin
function is selected without changing the configuration of the alternate peripheral. For example,
the A8/GPIOA0 pin shows that it is tri-stated during reset. If the GPIOA_PER is changed to select
the GPIO function of the pin, it will become an input if no other registers are changed.
Table 2-2 56F8355 Signal and Package Information for the 128-Pin LQFP
Signal Name
Pin No.
Type
State
During
Reset
Signal Description
VDD_IO
4
Supply
I/O Power — This pin supplies 3.3V power to the chip I/O
interface.
VDD_IO
14
VDD_IO
25
VDD_IO
36
VDD_IO
62
VDD_IO
76
VDD_IO
112
VDDA_ADC
94
Supply
ADC Power — This pin supplies 3.3V power to the ADC
modules. It must be connected to a clean analog power
supply.
VDDA_OSC_PLL
72
Supply
Oscillator and PLL Power — This pin supplies 3.3V
power to the OSC and to the internal regulator that in turn
supplies the Phase Locked Loop. It must be connected to
a clean analog power supply.
VSS
3
Supply
VSS — These pins provide ground for chip logic and I/O
drivers.
VSS
21
VSS
35
VSS
59
VSS
65
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