參數(shù)資料
型號: MC56F8355MFG60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 4-BIT, 120 MHz, OTHER DSP, PQFP128
封裝: LQFP-128
文件頁數(shù): 61/152頁
文件大小: 2224K
代理商: MC56F8355MFG60
16
56F8355 Technical Data
Preliminary
CLKO
3
Output
Tri-Stated
Clock Output — This pin outputs a buffered clock signal.
Using the SIM CLKO Select Register (SIM_CLKOSR), this
pin can be programmed as any of the following: disabled,
CLK_MSTR (system clock), IPBus clock, oscillator output,
prescaler clock and postscaler clock. Other signals are
also available for test purposes.
See Section 6.5.7 for details.
A8
(GPIOA0)
15
Output
Schmitt
Input/
Output
Tri-stated
Input
Address Bus— A8 - A13 specify six of the address lines
for external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), A8 - A13 and EMI control signals
are tri-stated when the external bus is inactive.
Port A GPIO — These six GPIO pins can be individually
programmed as input or output pins.
After reset, these pins default to address bus functionality
and must be programmed as GPIO.
To deactivate the internal pull-up resistor, clear the
appropriate GPIO bit in the GPIOA_PUR register.
Example: GPIOA0, clear bit 0 in the GPIOA_PUR register.
Note: Primary function is not available in this package
configuration; GPIO function must be used instead.
A9
(GPIOA1)
16
A10
(GPIOA2)
17
A11
(GPIOA3)
18
A12
(GPIOA4)
19
A13
(GPIOA5)
20
GPIOB0
(A16)
27
Schmitt
Input/
Output
Input
Tri-stated
Port B GPIO — These four GPIO pins can be
programmed as input or output pins.
Address Bus — A16 - A19 specify four of the address
lines for external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), A16 - A19 and EMI control signals
are tri-stated when the external bus is inactive.
After reset, the default state is GPIO.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOB_PUR register.
Example: GPIOB1, clear bit 1 in the GPIOB_PUR register.
GPIOB1
(A17)
28
GPIOB2
(A18)
29
GPIOB3
(A19)
30
Table 2-2 56F8355 Signal and Package Information for the 128-Pin LQFP
Signal Name
Pin No.
Type
State
During
Reset
Signal Description
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